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1. general description the lpc11axx are an arm cortex-m0 based, low-cost 32-bit mcu family, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduc ed code size compared to existing 8/16-bit architectures. the lpc11axx operate at cpu frequencies of up to 50 mhz. analog/mixed-signal subsystems can be configured by software from interconnected digital and analog peripherals. the digital peripherals on the lpc11axx include up to 32 kb of flash memory, up to 4 kb of eeprom data memory, up to 8 kb of sr am data memory, a fast-mode plus i 2 c-bus interface, a rs-485/eia-485 usart, tw o ssp controllers, four general purpose counter/timers, and up to 42 general purpose i/o pins. analog peripherals include a 10-bit adc, a 10-bit dac, an analog comparator, a temperature sensor, an internal voltage reference, and undervoltage lockout (uvlo) protection. 2. features and benefits ? system: ? arm cortex-m0 processor, running at frequencies of up to 50 mhz. ? arm cortex-m0 built-in nested vectored interrupt controller (nvic). ? serial wire debug (swd) ? jtag boundary scan. ? system tick timer. ? memory: ? up to 32 kb on-chip flash program memory. ? up to 4 kb on-chip eeprom data memory; byte erasable an d byte programmable. ? up to 8 kb sram data memory. ? 16 kb boot rom. ? in-system programming (isp) for flash and in-application programming (iap) for flash and eeprom via on-chip bootloader software. ? includes rom-based 32-bit integer division and i 2 c-bus driver routines. ? digital peripherals: ? up to 42 general purpose i/o (gpio) pi ns with configurable pull-up/pull-down resistors, repeater mode, and open-drain mode. lpc11axx 32-bit arm cortex-m0 microcontroller; up to 32 kb flash, 8 kb sram, 4 kb eeprom; configurable analog/mixed-signal rev. 4 ? 30 october 2012 product data sheet
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 2 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller ? up to 16 pins are configurable with a digita l input glitch filter for removing glitches with widths of 10 ns or less and two pins are configurable for 50 ns glitch filters. ? gpio pins can be used as edge and level sensitive interrupt sources. ? high-current source output driver (20 ma) on one pin (pio0_21). ? high-current sink driver (20 ma) on true open-drain pins (pio0_2 and pio0_3). ? four general purpose counter/timers with a total of up to 16 capture inputs and 14 match outputs. ? programmable windowed watchdog timer (wwdt) with a dedicated, internal low-power watchdog oscillator (wdosc). ? analog peripherals: ? 10-bit adc with input multiplexing among 8 pins. ? 10-bit dac with flexible conversion triggering. ? highly flexible analog comparator with a programmable voltage reference. ? integrated temperature sensor. ? internal voltage reference. ? undervoltage lockout (uvlo) protection against power-supply droop below 2.4 v. ? serial interfaces: ? usart with fractional baud rate gener ation, internal fifo, support for rs-485/9-bit mode and synchronous mode. ? two ssp controllers with fifo and multi-protocol capabilit ies. support data rates of up to 25 mbit/s. ? i 2 c-bus interface supporting the full i 2 c-bus specification and fast-mode plus with a data rate of 1 mbit/s with multiple address recognition and monitor mode. ? clock generation: ? crystal oscillator (sysosc) with an operating range of 1 mhz to 25 mhz. ? 12 mhz internal rc oscillator (irc) trimmed to 1% accuracy that can optionally be used as a system clock. ? internal low-power, low-frequency os cillator (lfosc) with programmable frequency output. ? clock input for external syste m clock (25 mhz typical). ? pll allows cpu operation up to the maxi mum cpu rate with the irc, the external clock, or the sysosc as clock sources. ? clock output function with divider that ca n reflect the sysosc, the irc, the main clock, or the lfosc. ? power control: ? supports one reduced power mode: the arm sleep mode. ? power profiles residing in boot rom allowing to optimize performance and minimize power consumption for any given application through one simple function call. ? processor wake-up from reduced power mode using any interrupt. ? power-on reset (por). ? brown-out detect (bod) with two programmable thresholds for interrupt and one hardware controlled reset trip point. ? por and bod are always enabled for rapid uvlo protection against power supply voltage droop below 2.4 v. ? unique device serial number for identification.
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 3 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller ? single 3.3 v power supply (2.6 v to 3.6 v). ? temperature range ? 40 ? c to +85 ? c. ? available as lqfp48 package, hvqfn33 ( 7 ? 7 ) and hvqfn33 ( 5 ? 5 ) packages, and in a very small wlcsp20 package. 3. applications 4. ordering information ? power management ? gaming equipment ? industrial control ? motion control ? remote monitoring ? medical instrumentation ? point-of-sale ? fire and security ? test and measurement equipment ? sensors ? network appliances and services ? precision instrumentation ? factory automation ? hvac and building control table 1. ordering information type number package name description version LPC11A02UK wlcsp20 wafer level chip-size package; 20 bumps; 2.5 ? 2.5 ? 0.6 mm - lpc11a04uk wlcsp20 wafer level chip-size package; 20 bumps; 2.5 ? 2.5 ? 0.6 mm - lpc11a11fhn33/001 hvqfn33 hvqfn: plastic thermal e nhanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a lpc11a12fhn33/101 hvqfn33 hvqfn: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a lpc11a13fhi33/201 hvqfn33 hvqfn: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 5 ? 5 ? 0.85 mm n/a lpc11a14fhn33/301 hvqfn33 hvqfn: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a lpc11a12fbd48/101 lqfp48 lqfp48: plastic low pr ofile quad flat package; 48 leads; body 7 ? 7 ? 1.4 mm sot313-2 lpc11a14fbd48/301 lqfp48 lqfp48: plastic low pr ofile quad flat package; 48 leads; body 7 ? 7 ? 1.4 mm sot313-2
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 4 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller 4.1 ordering options table 2. ordering options type number flash sram eeprom 10-bit adc channels 10-bit dac temperature sensor analog comparator usart ssp/spi i 2 c gpio package LPC11A02UK 16 kb 4 kb 2 kb 8 1 1 1 1 1 1 18 wlcsp20 lpc11a04uk 32 kb 8 kb 4 kb 8 1 1 1 1 1 1 18 wlcsp20 lpc11a11fhn33/001 8 kb 2 kb 512 b 8 1 1 1 1 2 1 28 hvqfn33 lpc11a12fhn33/101 16 kb 4 kb 1 kb 8 1 1 1 1 2 1 28 hvqfn33 lpc11a12fbd48/101 16 kb 4 kb 1 kb 8 1 1 1 1 2 1 42 lqfp48 lpc11a13fhi33/201 24 kb 6 kb 2 kb 8 1 1 1 1 2 1 28 hvqfn33 lpc11a14fhn33/301 32 kb 8 kb 4 kb 8 1 1 1 1 2 1 28 hvqfn33 lpc11a14fbd48/301 32 kb 8 kb 4 kb 8 1 1 1 1 2 1 42 lqfp48
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 5 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller 5. block diagram (1) open-drain pins. (2) standard i/o pins. (3) not available on wlcsp packages. (4) modem control pins not available on wlcsp packages. fig 1. lpc11axx block diagram sram 2/4/6/8 kb arm cortex-m0 test/debug interface flash 8/16/24/32 kb eeprom 512 b/ 1/4 kb high-speed gpio ahb to apb bridge clock generation, power control, system functions reset clocks, internal voltage reference, and controls swd lpc11axx 002aaf428 slave slave slave slave rom 16 kb slave ahb-lite bus gpio ports clkout clkin irc, lfosc, wdosc sysosc (3) por bod analog comparator 10-bit adc usart (4) 32-bit counter/timer 0 ct32b0_mat[3:0] ad[7:0] aout ct32b0_cap[2:0] rxd txd rts, dtr sclk pmu system control 32-bit counter/timer 1 ct32b1_mat[3:0] ct32b1_cap[2:0] cts, dcd, dsr, ri atrg[1:0] acmp_i[5:1] acmp_o vddcmp 16-bit counter/timer 1 windowed watchdog timer ct16b1_mat[3:0] 16-bit counter/timer 0 ct16b0_mat[3:0] ct16b0_cap[2:0] ct16b1_cap[2:0] 10-bit dac system bus temperature sensor ssp0 sck0, ssel0, miso0, mosi0 ssp1 (3) sck1, ssel1, miso1, mosi1 i 2 c-bus ioconfig scl, sda (2) scl, sda (2) scl, sda (1) scl, sda (2) xtalin xtalout
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 6 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller 6. pinning information 6.1 pinning fig 2. pin configuration lqfp48 package lpc11a12fbd48/101 lpc11a14fbd48/301 pio0_26 pio1_1 pio0_28 trst/pio0_9 reset/pio0_0 tdo/pio0_8 pio0_1 tms/pio0_7 v ss(io) tdi/pio0_6 xtalin pio1_0 xtalout pio0_14 v dd(io) tck/swclk/pio0_5 pio0_24 pio0_4 pio0_18 pio0_22 pio1_6 pio1_8 pio1_9 pio1_7 pio0_29 pio1_3 pio0_19 pio0_13 pio0_2 pio0_12 pio0_3 pio0_23 pio0_25 v dd(3v3) pio0_16 pio0_27 pio1_4 v ss pio1_5 pio0_15 pio0_17 pio0_30 pio0_20 pio0_11 pio0_21 pio0_31 swdio/pio0_10 pio1_2 002aaf499 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 48 47 46 45 44 43 42 41 40 39 38 37 24
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 7 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller 6.2 pin description all functional pins on the lpc11axx are mapped to gpio port 0 and port 1 (see table 4 ). the port pins are multiplexed to ac commodate more than one function (see table 3 ). the pin function is controlled by the pin?s iocon register (see the lpc11axx user manual ). the standard i/o pad conf iguration is illustrated in figure 31 and a detailed pin description is given in ta b l e 4 . parts: lpc11a11fhn33/001, lpc11a12fhn33/101, lpc11a13fhi33/201, lpc11a14fhn33/301 fig 3. pin configuration hvqfn 33 package parts: LPC11A02UK, lpc11a04uk fig 4. pin configuration wlcsp20 package 002aaf500 transparent top view pio0_22 pio0_24 pio0_18 pio0_4 v dd(io) tck/swclk/pio0_5 xtalout pio0_14 xtalin tdi/pio0_6 pio0_1 tms/pio0_7 reset/pio0_0 tdo/pio0_8 pio0_26 trst/pio0_9 pio0_19 pio0_2 pio0_3 pio0_25 pio0_16 pio0_17 pio0_20 pio0_21 pio0_13 pio0_12 pio0_23 v dd(3v3) pio0_27 pio0_15 pio0_11 swdio/pio0_10 8 17 7 18 6 19 5 20 4 21 3 22 2 23 1 24 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 terminal 1 index area 33 v ss 002aaf175 e d c b a 1234
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 8 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller table 3. pin multiplexing function type lqfp48 hvqfn33 wcsp20 port glitch filter pin pin ball system clocks, reset, and wake-up clkin i pio0_1 no 4 3 b2 pio0_12 no 46 31 e1 pio0_19 no 14 9 - pio0_24 no 9 7 - clkout o pio0_1 no 4 3 b2 pio0_19 no 14 9 - xtalin i (analog) --64- xtalout o (analog) --75- reset i pio0_0 20 ns [1] 32c 1 serial wire debug (swd) and jtag trst i pio0_9 10 ns [2] 35 24 d4 tck i pio0_5 10 ns [2] 29 19 b3 tdi i pio0_6 10 ns [2] 32 21 c3 tdo o pio0_8 no 34 23 c2 tms i pio0_7 10 ns [2] 33 22 c4 swclk i pio0_2 50 ns [2] 15 10 a1 pio0_5 10 ns [2] 29 19 b3 swdio i/o pio0_3 50 ns [2] 16 11 b1 pio0_10 10 ns [2] 38 25 d3 analog peripherals ( adc, dac, comparator) acmp_i1 i (analog) pio0_27 no 43 28 - acmp_i2 i (analog) pio0_13 no 47 32 d1 acmp_i3 i (analog) pio0_16 no 18 13 a2 acmp_i4 i (analog) pio0_17 no 21 14 a3 acmp_i5 i (analog) pio0_22 no 27 17 - acmp_o o (digital) pio0_2 no 15 10 a1 pio0_3 no 16 11 b1 pio0_12 no 46 31 e1 pio0_21 no 23 16 - pio0_23 no 45 30 - ad0 i (analog) pio0_6 no 32 21 c3 ad1 i (analog) pio0_7 no 33 22 c4
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 9 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller ad2 i (analog) pio0_8 no 34 23 c2 ad3 i (analog) pio0_9 no 35 24 d4 ad4 i (analog) pio0_10 no 38 25 d3 ad5 i (analog) p i o 0 _ 1 1n o3 92 6d 2 ad6 i (analog) pio0_14 no 30 20 b4 ad7 i (analog) pio0_15 no 41 27 e4 aout o (analog) pio0_4 no 28 18 a4 atrg0 i pio0_16 10 ns [2] 18 13 a2 atrg1 i pio0_17 10 ns [2] 21 14 a3 vddcmp i (analog) pio0_14 no 30 20 - pio0_5 no - - b3 i 2 c-bus interface scl i/o pio0_2 50 ns [2] 15 10 a1 pio0_12 no 46 31 e1 pio0_16 10 ns [2] 18 13 a2 pio0_24 no 9 7 - sda i/o pio0_3 50 ns [2] 16 11 b1 pio0_13 10 ns [2] 47 32 d1 pio0_15 10 ns [2] 41 27 e4 pio0_25 no 17 12 - ssp0 controller miso0 i/o pio0_6 10 ns [2] 32 21 c3 pio0_22 10 ns [2] 27 17 - pio1_2 no 37 - - mosi0 i/o pio0_4 10 ns [2] 28 18 a4 pio0_19 no 14 9 - pio1_3 no 48 - - pio1_7 no 25 - - sck0 i/o pio0_5 10 ns [2] 29 19 b3 pio0_20 no 22 15 - pio1_0 no 31 - - ssel0 i/o pio0_1 no 4 3 b2 pio0_18 no 10 8 - pio1_1 no 36 - - table 3. pin multiplexing function type lqfp48 hvqfn33 wcsp20 port glitch filter pin pin ball
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 10 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller ssp1 controller miso1 i/o pio0_14 10 ns [2] 30 20 - pio0_26 no 1 1 - pio1_8 no 26 - - mosi1 i/o pio0_27 10 ns [2] 43 28 - pio0_31 no 24 - - pio0_30 no 40 - - pio1_6 no 11 - - sck1 i/o pio0_8 10 ns [2] 34 23 - pio1_5 no 20 - - pio0_29 no 13 - - ssel1 i/o pio0_25 no 17 12 - pio1_4 no 19 - - pio0_28 no 2 - - usart rxd i pio0_1 no 4 3 b2 pio0_12 no 46 31 e1 pio1_4 no 19 - - pio1_8 no 26 - - txd o pio0_13 no 47 32 d1 pio0_15 no 41 27 e4 pio0_26 no 1 1 - pio1_5 no 20 - - sclk i/o pio0_11 10 ns [2] 39 26 d2 pio0_21 no 23 16 - pio0_23 no 45 30 - cts i pio0_9 10 ns [2] 35 24 d4 pio0_21 no 23 16 - pio1_7 no 25 - - rts o pio0_10 no 38 25 d3 pio0_23 no 45 30 - pio1_6 no 11 - - dcd ipio1_9no 12 - - pio1_0 no 31 - - dsr i pio0_29 no 13 - - pio1_2 no 37 - - dtr o pio0_28 no 2 - - pio1_1 no 36 - - table 3. pin multiplexing function type lqfp48 hvqfn33 wcsp20 port glitch filter pin pin ball
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 11 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller ri i pio0_30 no 40 - - pio0_31 no 24 - - pio1_3 no 48 - - 16-bit counte r/timer ct16b0 ct16b0_cap0 i pio0_2 50 ns [2] 15 10 a1 pio0_18 no 10 8 - pio0_30 no 40 - - ct16b0_cap1 i pio0_16 10 ns [2] 18 13 a2 pio1_4 no 19 - - ct16b0_cap2 i pio0_17 10 ns [2] 21 14 a3 pio1_5 no 20 - - ct16b0_mat0 o pio0_7 no 33 22 c4 pio0_17 no 21 14 a3 pio1_6 no 11 - - ct16b0_mat1 o pio0_4 no 28 18 a4 pio0_9 no 35 24 d4 pio1_0 no 31 - - ct16b0_mat2 o pio0_5 no 29 19 b3 pio0_10 no 38 25 d3 pio1_7 no 25 - - 16-bit counte r/timer ct16b1 ct16b1_cap0 i pio0_3 50 ns [2] 16 11 b1 pio0_24 no 9 7 - pio1_3 no 48 - - ct16b1_cap1 i pio0_18 no 10 8 - pio0_26 no 1 1 - pio0_31 no 24 - - ct16b1_cap2 i pio0_27 10 ns [2] 43 28 - pio1_7 no 25 - - ct16b1_mat0 o pio0_19 no 14 9 - pio0_25 no 17 12 - pio1_1 no 36 - - ct16b1_mat1 o pio0_14 no 30 20 b4 pio1_2 no 37 - - pio1_8 no 26 - - ct16b1_mat2 o pio0_20 no 22 15 - pio1_2 no 37 - - pio1_9 no 12 - - table 3. pin multiplexing function type lqfp48 hvqfn33 wcsp20 port glitch filter pin pin ball
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 12 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller 32-bit counte r/timer ct32b0 ct32b0_cap0 i pio0_11 10 ns [2] 39 26 d2 pio0_23 no 45 30 - pio0_28 no 2 - - ct32b0_cap1 i pio0_14 10 ns [2] 30 20 b4 pio0_29 no 13 - - ct32b0_cap2 i pio0_15 10 ns [2] 41 27 e4 pio0_26 no 1 1 - ct32b0_mat0 o pio0_12 no 46 31 e1 pio0_30 no 40 - - ct32b0_mat1 o pio0_13 no 47 32 d1 pio1_4 no 19 - - ct32b0_mat2 o pio0_1 no 4 3 b2 pio1_5 no 20 - - ct32b0_mat3 o pio0_6 no 32 21 c3 pio1_6 no 11 - - 32-bit counte r/timer ct32b1 ct32b1_cap0 i pio0_7 10 ns [2] 33 22 c4 pio0_20 no 22 15 - pio1_4 no 19 - - ct32b1_cap1 i pio0_21 no 23 16 - pio1_5 no 20 - - ct32b1_cap2 i pio0_22 10 ns [2] 27 17 - pio1_6 no 11 - - ct32b1_mat0 o pio0_8 no 34 23 c2 pio0_31 no 24 - - pio1_8 no 26 - - ct32b1_mat1 o pio0_9 no 35 24 d4 pio0_27 no 43 28 - pio1_7 no 25 - - ct32b1_mat2 o pio0_10 no 38 25 d3 pio0_22 no 27 17 - pio1_9 no 12 - - ct32b1_mat3 o pio0_11 no 39 26 d2 pio1_1 no 36 - - pio1_0 no 31 - - supply and ground pins v dd(io) supply - - 8 6 e2 table 3. pin multiplexing function type lqfp48 hvqfn33 wcsp20 port glitch filter pin pin ball
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 13 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller [1] always on. [2] programmable on/off. by default, the glitch filter is disabled. ta b l e 4 shows all pins in order of their port nu mber. the default function after reset is listed first. all port pins pio0_0 to pio1_9 have internal pull-up resistors enabled after reset with the exception of the true open-drain pins pio0_2 and pio0_3. pull-up/pull-down configuration, repeater, and open-drain modes can be programmed through the iocon registers for each of the port pins. v dd(3v3) supply - - 44 29 e2 v ss ground - - 42 33 e3 v ss(io) ground - - 5 33 e3 table 3. pin multiplexing function type lqfp48 hvqfn33 wcsp20 port glitch filter pin pin ball table 4. lpc11axx pin description table symbol pin/ball type reset state [1] description lqfp48 hvqfn33 wlcsp20 reset /pio0_0 3 2 c1 [2] ii; pu reset ? external reset input with fixed 20 ns glitch filter: a low on this pin resets the device, causing i/o ports and peripherals to take on their default states and processor execution to begin at address 0. i/o - pio0_0 ? general purpose digital input/output pin. pio0_1/rxd/clkout/ ct32b0_mat2/ssel0/ clkin 43b2 [3] i/o i; pu pio0_1 ? general purpose digital in put/output pin. a low level on this pin during reset starts the isp command handler. i- rxd ? receiver data input for usart. o- clkout ? clock output. o- ct32b0_mat2 ? match output 2 for 32-bit timer 0. i/o - ssel0 ? slave select for ssp0. i- clkin ? external clock input. pio0_2/scl/acmp_o/ tck/swclk/ ct16b0_cap0 15 10 a1 [4] [5] i/o i; ia pio0_2 ? general purpose digital input/output pin. high-current sink (20 ma) or standard-current sink (4 ma) programmable; true open-drain for all pin functions. input glitch filter (50 ns) capable. i/o - scl ? i 2 c-bus clock (true open-drai n) input/output. input glitch filter (50 ns) capable. o- acmp_o ? analog comparator output. i- tck/swclk ? serial wire debug clock (secondary for lqfp and hvqfn packages). i nput glitch filter (50 ns) capable. for the wlcsp20 package only, this pin is configured to the swclk function by the boot loader after reset. i- ct16b0_cap0 ? capture input 0 for 16-bit timer 0. input glitch filter (50 ns) capable.
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 14 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller pio0_3/sda/acmp_o/ swdio/ct16b1_cap0 16 11 b1 [4] [6] i/o i; ia pio0_3 ? general purpose digital input/output pin. high-current sink (20 ma) or standard-current sink (4 ma) programmable; true open-drain for all pin functions. input glitch filter (50 ns) capable. i/o - sda ? i 2 c-bus data (true open-drai n) input/output. input glitch filter (50 ns) capable. o- acmp_o ? analog comparator output. i/o - swdio ? serial wire debug i/o (secondary for lqfp and hvqfn packages). input glitch f ilter (50 ns) capable. for the wlcsp20 package only, this pin is configured to the swdio function by the boot loader after reset. i- ct16b1_cap0 ? capture input 0 for 16-bit timer 1. input glitch filter (50 ns) capable. pio0_4/r/aout/ ct16b0_mat1/mosi0 28 18 a4 [7] i/o i; pu pio0_4 ? general purpose digital input/output pin. input glitch filter (10 ns) capable. -- r ? reserved. o- aout ? d/a converter output. o- ct16b0_mat1 ? match output 1 for 16-bit timer 0. i/o - mosi0 ? master out slave in for ssp0. input glit ch filter (10 ns) capable. tck/swclk/pio0_5/ r/ct16b0_mat2/ sck0 29 19 - [9] ii; pu tck/swclk ? test clock tck for jtag interface and primary (default) serial wire deb ug clock. input glitch filter (10 ns) capable. i/o - pio0_5 ? general purpose digital input/output pin. input glitch filter (10 ns) capable. -- r ? reserved. o- ct16b0_mat2 ? match output 2 for 16-bit timer 0. i/o - sck0 ? serial clock for ssp0. inpu t glitch filter (10 ns) capable. tck/swclk/pio0_5/ vddcmp/ ct16b0_mat2/ sck0 --b3 [7] [8] ii; pu tck/swclk ? test clock tck for jtag interface and secondary serial wire debug clock. use pio0_2 for the default tck/swclk function. input glitch filter (10 ns) capable. i/o - pio0_5 ? general purpose digital input/output pin. input glitch filter (10 ns) capable. i- vddcmp ? analog comparator alternate reference voltage. o- ct16b0_mat2 ? match output 2 for 16-bit timer 0. i/o - sck0 ? serial clock for ssp0. inpu t glitch filter (10 ns) capable. table 4. lpc11axx pin description table symbol pin/ball type reset state [1] description lqfp48 hvqfn33 wlcsp20
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 15 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller tdi/pio0_6/ad0/ ct32b0_mat3/miso0 32 21 c3 [9] ii; pu tdi ? test data in for jtag interface. input glitch filter (10 ns) capable. i/o - pio0_6 ? general purpose digital input/output pin. input glitch filter (10 ns) capable. i- ad0 ? a/d converter input 0. o- ct32b0_mat3 ? match output 3 for 32-bit timer 0. i/o - miso0 ? master in slave out for ssp0. input glit ch filter (10 ns) capable. tms/pio0_7/ad1/ ct32b1_cap0/ ct16b0_mat0 33 22 c4 [9] ii; pu tms ? test mode select for jtag in terface. input glitch filter (10 ns) capable. i/o - pio0_7 ? general purpose digital input/output pin. input glitch filter (10 ns) capable. i- ad1 ? a/d converter input 1. i- ct32b1_cap0 ? capture input 0 for 32-bit timer 1. input glitch filter (10 ns) capable. o- ct16b0_mat0 ? match output 2 for 16-bit timer 0. tdo/pio0_8/ad2/ ct32b1_mat0/sck1 34 23 c2 [9] oi; pu tdo ? test data out for jtag interface. i/o - pio0_8 ? general purpose digital input/output pin. input glitch filter (10 ns) capable. i- ad2 ? a/d converter input 2. o- ct32b1_mat0 ? match output 0 for 32-bit timer 1. i/o - sck1 ? serial clock for ssp1. inpu t glitch filter (10 ns) capable. trst /pio0_9/ad3/ ct32b1_mat1/ ct16b0_mat1/cts 35 24 d4 [9] ii; pu trst ? test reset for jtag interf ace. input glitch filter (10 ns) capable. i/o - pio0_9 ? general purpose digital input/output pin. input glitch filter (10 ns) capable. i- ad3 ? a/d converter, input 3. o- ct32b1_mat1 ? match output 1 for 32-bit timer 1. o- ct16b0_mat1 ? match output 1 for 16-bit timer 0. i- cts ? clear to send input for usart. input glitch filter (10 ns) capable. table 4. lpc11axx pin description table symbol pin/ball type reset state [1] description lqfp48 hvqfn33 wlcsp20
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 16 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller swdio/pio0_10/ad4/ ct32b1_mat2/ ct16b0_mat2/rts 38 25 d3 [9] i/o i; pu swdio ? primary (default) serial wire debug i/o for the lqfp48 and hvqfn33 packages. for the wlcsp20 package, use pio0_3. input glitch filter (10 ns) capable. i/o - pio0_10 ? general purpose digital input/output pin. input glitch filter (10 ns) capable. i- ad4 ? a/d converter, input 4. o- ct32b1_mat2 ? match output 2 for 32-bit timer 1. o- ct16b0_mat2 ? match output 2 for 16-bit timer 0. o- rts ? request to send output for usart. pio0_11/sclk/ ad5/ct32b1_mat3/ ct32b0_cap0 39 26 d2 [9] i/o i; pu pio0_11 ? general purpose digital input/output pin. input glitch filter (10 ns) capable. i/o - sclk ? serial clock for usart. input glitch filter (10 ns) capable. i- ad5 ? a/d converter, input 5. o- ct32b1_mat3 ? match output 3 for 32-bit timer 1. i- ct32b0_cap0 ? capture input 0 for 32-bit timer 0. input glitch filter (10 ns) capable. pio0_12/rxd/ acmp_o/ ct32b0_mat0/scl/ clkin 46 31 e1 [3] i/o i; pu pio0_12 ? general purpose digi tal input/output pin. i- rxd ? receiver data input for usart. this pin is used for isp communication. o- acmp_o ? analog comparator output. o- ct32b0_mat0 ? match output 0 for 32-bit timer 0. i/o - scl ? i 2 c-bus clock input/output. this is not an i 2 c-bus open-drain pin [10] . i- clkin ? external clock input. pio0_13/txd/ acmp_i2/ ct32b0_mat1/sda 47 32 d1 [9] i/o i; pu pio0_13 ? general purpose digital input/output pin. input glitch filter (10 ns) capable. o- txd ? transmitter data output for usart. this pin is used for isp communication. i- acmp_i2 ? analog comparator input 2. o- ct32b0_mat1 ? match output 1 for 32-bit timer 0. i/o - sda ? i 2 c-bus data input/output. this is not an i 2 c-bus open-drain pin [10] . input glitch filter (10 ns) capable. table 4. lpc11axx pin description table symbol pin/ball type reset state [1] description lqfp48 hvqfn33 wlcsp20
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 17 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller pio0_14/miso1/ad6/ ct32b0_cap1/ ct16b1_mat1/ vddcmp 30 20 - [7] i/o i; pu pio0_14 ? general purpose digital input/output pin. input glitch filter (10 ns) capable. i/o - miso1 ? master in slave out for ssp1. input glit ch filter (10 ns) capable. i- ad6 ? a/d converter, input 6. i- ct32b0_cap1 ? capture input 1 for 32-bit timer 0. input glitch filter (10 ns) capable. o- ct16b1_mat1 ? match output 1 for 16-bit timer 1. i- vddcmp ? analog comparator alternate reference voltage. pio0_14/miso1/ad6/ ct32b0_cap1/ ct16b1_mat1 --b4 [9] i/o i; pu pio0_14 ? general purpose digital input/output pin. input glitch filter (10 ns) capable. i/o - miso1 ? master in slave out for ssp1. input glit ch filter (10 ns) capable. i- ad6 ? a/d converter, input 6. i- ct32b0_cap1 ? capture input 1 for 32-bit timer 0. input glitch filter (10 ns) capable. o- ct16b1_mat1 ? match output 1 for 16-bit timer 1. pio0_15/txd/ad7/ ct32b0_cap2/sda 41 27 e4 [9] i/o i; pu pio0_15 ? general purpose digital input/output pin. input glitch filter (10 ns) capable. o- txd ? transmitter data output for usart. i- ad7 ? a/d converter, input 7. i- ct32b0_cap2 ? capture input 2 for 32-bit timer 0. input glitch filter (10 ns) capable. i/o - sda ? i 2 c-bus data input/output. this is not an i 2 c-bus open-drain pin [10] . input glitch filter (10 ns) capable. pio0_16/ atrg0/acmp_i3/ ct16b0_cap1/scl 18 13 a2 [9] i/o i; pu pio0_16 ? general purpose digital input/output pin. input glitch filter (10 ns) capable. i- atrg0 ? conversion trigger 0 for adc or dac. input glitch filter (10 ns) capable. i- acmp_i3 ? analog comparator input 3. i- ct16b0_cap1 ? capture input 1 for 16-bit timer 0. input glitch filter (10 ns) capable. i/o - scl ? i 2 c-bus clock input/output. this is not an i 2 c-bus open-drain pin [10] . input glitch filter (10 ns) capable. table 4. lpc11axx pin description table symbol pin/ball type reset state [1] description lqfp48 hvqfn33 wlcsp20
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 18 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller pio0_17/ atrg1/acmp_i4/ ct16b0_cap2/ ct16b0_mat0 21 14 a3 [9] i/o i; pu pio0_17 ? general purpose digital input/output pin. input glitch filter (10 ns) capable. i- atrg1 ? conversion trigger 1 for adc or dac. input glitch filter (10 ns) capable. i- acmp_i4 ? analog comparator input 4. i- ct16b0_cap2 ? capture input 2 for 16-bit timer 0. input glitch filter (10 ns) capable. o- ct16b0_mat0 ? match output 0 for 16-bit timer 0. pio0_18/r/ssel0/ ct16b0_cap0/ ct16b1_cap1 10 8 - [3] i/o i; pu pio0_18 ? general purpose digi tal input/output pin. -- r ? reserved. i/o - ssel0 ? slave select for ssp0. i- ct16b0_cap0 ? capture input 0 for 16-bit timer 0. i- ct16b1_cap1 ? capture input 1 for 16-bit timer 1. pio0_19/clkin/ clkout/ mosi0/ct16b1_mat0 14 9 - [3] i/o i; pu pio0_19 ? general purpose digi tal input/output pin. i- clkin ? external clock input. o- clkout ? clock output. i/o - mosi0 ? master out slave in for ssp0. o- ct16b1_mat0 ? match output 0 for 16-bit timer 1. pio0_20/r/sck0/ ct32b1_cap0/ ct16b1_mat2 22 15 - [3] i/o i; pu pio0_20 ? general purpose digi tal input/output pin. -- r ? reserved. i/o - sck0 ? serial clock for ssp0. i- ct32b1_cap0 ? capture input 0 for 32-bit timer 1. o- ct16b1_mat2 ? match output 2 for 16-bit timer 1. pio0_21/cts / acmp_o/ ct32b1_cap1/sclk 23 16 - [3] i/o i; pu pio0_21 ? general purpose digital input/output pin. if configured as output, this pin is a high-current source output driver (20 ma). i- cts ? clear to send input for usart. o- acmp_o ? analog comparator output. i- ct32b1_cap1 ? capture input 1 for 32-bit timer 1. i/o - sclk ? serial clock for usart. pio0_22/miso0/ acmp_i5/ ct32b1_mat2/ ct32b1_cap2 27 17 - [9] i/o i; pu pio0_22 ? general purpose digital input/output pin. input glitch filter (10 ns) capable. i/o - miso0 ? master in slave out for ssp0. input glit ch filter (10 ns) capable. i- acmp_i5 ? analog comparator input 5. o- ct32b1_mat2 ? match output 2 for 32-bit timer 1. i- ct32b1_cap2 ? capture input 2 for 32-bit timer 1. input glitch filter (10 ns) capable. table 4. lpc11axx pin description table symbol pin/ball type reset state [1] description lqfp48 hvqfn33 wlcsp20
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 19 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller pio0_23/rts / acmp_o/ ct32b0_cap0/sclk 45 30 - [3] i/o i; pu pio0_23 ? general purpose digi tal input/output pin. o- rts ? request to send output for usart. o- acmp_o ? analog comparator output. i- ct32b0_cap0 ? capture input 0 for 32-bit timer 0. i/o - sclk ? serial clock for usart. pio0_24/scl/clkin/ ct16b1_cap0 97- [3] i/o i; pu pio0_24 ? general purpose digi tal input/output pin. i/o - scl ? i 2 c-bus clock input/output. this is not an i 2 c-bus open-drain pin [10] . i- clkin ? external clock input. i- ct16b1_cap0 ? capture input 0 for 16-bit timer 1. pio0_25/sda/ssel1/ ct16b1_mat0 17 12 - [3] i/o i; pu pio0_25 ? general purpose digi tal input/output pin. i/o - sda ? i 2 c-bus data input/output. this is not an i 2 c-bus open-drain pin [10] . i/o - ssel1 ? slave select for ssp1. o- ct16b1_mat0 ? match output 0 for 16-bit timer 1. pio0_26/txd/miso1/ ct16b1_cap1/ ct32b0_cap2 11- [3] i/o i; pu pio0_26 ? general purpose digi tal input/output pin. o- txd ? transmitter data output for usart. i/o - miso1 ? master in slave out for ssp1. i- ct16b1_cap1 ? capture input 1 for 16-bit timer 1. i- ct32b0_cap2 ? capture input 2 for 32-bit timer 0. pio0_27/mosi1/ acmp_i1/ ct32b1_mat1/ ct16b1_cap2 43 28 - [9] i/o i; pu pio0_27 ? general purpose digital input/output pin. input glitch filter (10 ns) capable. i/o - mosi1 ? master out slave in for ssp1. input glit ch filter (10 ns) capable. i- acmp_i1 ? analog comparator input 1. o- ct32b1_mat1 ? match output 1 for 32-bit timer 1. i- ct16b1_cap2 ? capture input 2 for 16-bit timer 1. input glitch filter (10 ns) capable. pio0_28/dtr /ssel1/ ct32b0_cap0 2- - [3] i/o i; pu pio0_28 ? general purpose digi tal input/output pin. o- dtr ? data terminal ready output for usart. i/o - ssel1 ? slave select for ssp1. i- ct32b0_cap0 ? capture input 0 for 32-bit timer 0. pio0_29/dsr /sck1/ ct32b0_cap1 13 - - [3] i/o i; pu pio0_29 ? general purpose digi tal input/output pin. i- dsr ? data set ready input for usart. i/o - sck1 ? serial clock for ssp1. i- ct32b0_cap1 ? capture input 1 for 32-bit timer 0. table 4. lpc11axx pin description table symbol pin/ball type reset state [1] description lqfp48 hvqfn33 wlcsp20
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 20 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller pio0_30/ri /mosi1/ ct32b0_mat0/ ct16b0_cap0 40 - - [3] i/o i; pu pio0_30 ? general purpose digi tal input/output pin. i- ri ? ring indicator input for usart. i/o - mosi1 ? master out slave in for ssp1. o- ct32b0_mat0 ? match output 0 for 32-bit timer 0. i- ct16b0_cap0 ? capture input 0 for 16-bit timer 0. pio0_31/ri /mosi1/ ct32b1_mat0/ ct16b1_cap1 24 - - [3] i/o i; pu pio0_31 ? general purpose digi tal input/output pin. i- ri ? ring indicator input for usart. i/o - mosi1 ? master out slave in for ssp1. o- ct32b1_mat0 ? match output 0 for 32-bit timer 1. i- ct16b1_cap1 ? capture input 1 for 16-bit timer 1. pio1_0/dcd /sck0/ ct32b1_mat3/ ct16b0_mat1 31 - - [3] i/o i; pu pio1_0 ? general purpose digital input/output pin. i- dcd ? data carrier detect input for usart. i/o - sck0 ? serial clock for ssp0. o- ct32b1_mat3 ? match output 3 for 32-bit timer 1. o- ct16b0_mat1 ? match output 1 for 16-bit timer 0. pio1_1/dtr /ssel0/ ct32b1_mat3/ ct16b1_mat0 36 - - [3] i/o i; pu pio1_1 ? general purpose digital input/output pin. o- dtr ? data terminal ready output for usart. i/o - ssel0 ? slave select for ssp0. o- ct32b1_mat3 ? match output 3 for 32-bit timer 1. o- ct16b1_mat0 ? match output 0 for 16-bit timer 1. pio1_2/dsr /miso0/ ct16b1_mat2/ ct16b1_mat1 37 - - [3] i/o i; pu pio1_2 ? general purpose digital input/output pin. i- dsr ? data set ready input for usart. i/o - miso0 ? master in slave out for ssp0. o- ct16b1_mat2 ? match output 2 for 16-bit timer 1. o- ct16b1_mat1 ? match output 1 for 16-bit timer 1. pio1_3/ri /mosi0/ ct16b1_cap0 48 - - [3] i/o i; pu pio1_3 ? general purpose digital input/output pin. i- ri ? ring indicator input for usart. i/o - mosi0 ? master out slave in for ssp0. i- ct16b1_cap0 ? capture input 0 for 16-bit timer 1. pio1_4/rxd/ssel1/ ct32b0_mat1/ ct32b1_cap0/ ct16b0_cap1 19 - - [3] i/o i; pu pio1_4 ? general purpose digital input/output pin. i- rxd ? receiver data input for usart. i/o - ssel1 ? slave select for ssp1. o- ct32b0_mat1 ? match output 1 for 32-bit timer 0. i- ct32b1_cap0 ? capture input 0 for 32-bit timer 1. i- ct16b0_cap1 ? capture input 1 for 16-bit timer 0. table 4. lpc11axx pin description table symbol pin/ball type reset state [1] description lqfp48 hvqfn33 wlcsp20
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 21 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller pio1_5/txd/sck1/ ct32b0_mat2/ ct32b1_cap1/ ct16b0_cap2 20 - - [3] i/o i; pu pio1_5 ? general purpose digital input/output pin. o- txd ? transmitter data output for usart. i/o - sck1 ? serial clock for ssp1. o- ct32b0_mat2 ? match output 2 for 32-bit timer 0. i- ct32b1_cap1 ? capture input 1 for 32-bit timer 1. i- ct16b0_cap2 ? capture input 2 for 16-bit timer 0. pio1_6/rts /mosi1/ ct32b0_mat3/ ct32b1_cap2/ ct16b0_mat0 11 - - [3] i/o i; pu pio1_6 ? general purpose digital input/output pin. o- rts ? request to send output for usart. i/o - mosi1 ? master out slave in for ssp1. o- ct32b0_mat3 ? match output 3 for 32-bit timer 0. i- ct32b1_cap2 ? capture input 2 for 32-bit timer 1. o- ct16b0_mat0 ? match output 0 for 16-bit timer 0. pio1_7/cts /mosi0/ ct32b1_mat1/ ct16b0_mat2/ ct16b1_cap2 25 - - [3] i/o i; pu pio1_7 ? general purpose digital input/output pin. i- cts ? clear to send input for usart. i/o - mosi0 ? master out slave in for ssp0. o- ct32b1_mat1 ? match output 1 for 32-bit timer 1. o- ct16b0_mat2 ? match output 2 for 16-bit timer 0. i- ct16b1_cap2 ? capture input 2 for 16-bit timer 1. pio1_8/rxd / miso1/ ct32b1_mat0/ ct16b1_mat1 26 - - [3] i/o i; pu pio1_8 ? general purpose digital input/output pin. i- rxd ? receiver data input for usart. i/o - miso1 ? master in slave out for ssp1. o- ct32b1_mat0 ? match output 0 for 32-bit timer 1. o- ct16b1_mat1 ? match output 1 for 16-bit timer 1. pio1_9/dcd /r/ ct32b1_mat2 / ct16b1_mat2 12 - - [3] i/o i; pu pio1_9 ? general purpose digital input/output pin. i- dcd ? data carrier detect input for usart. -- r ? reserved. o- ct32b1_mat2 ? match output 2 for 32-bit timer 1. o- ct16b1_mat2 ? match output 2 for 16-bit timer 1. xtalin 6 4 - [11] - - input to the oscillator circuit and internal clock generator circuits. input voltage must not exceed 1.8 v. xtalout 7 5 - [11] - - output from the oscillator amplifier. v dd(io) 86e2 [12] [13] - - 3.3 v input/output supply voltage. table 4. lpc11axx pin description table symbol pin/ball type reset state [1] description lqfp48 hvqfn33 wlcsp20
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 22 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller [1] pin state at reset for default function: i = input; o = out put; pu = internal pull-up resistor (weak pmos device) enabled; i a = inactive, no pull-up/down enabled. [2] see figure 32 for the reset configuration. [3] 5 v tolerant pin providing standard digital i/o functions with configurable modes an d configurable hysteresis ( figure 31 ). [4] i 2 c-bus pins compliant with the i 2 c-bus specification for i 2 c standard mode, i 2 c fast-mode, and i 2 c fast-mode plus. [5] for the swd function, a pull-up resistor is recommended for the swclk pin (wlcsp20 parts only). [6] for the swd function, a pull-up resistor is recommended for the swdio pin (wlcsp20 parts only). [7] not a 5 v tolerant pin due to special analog functionality. pi n provides standard digital i/o functions with configurable mo des, configurable hysteresis, and analog i/o. w hen configured as an analog i/o, the digi tal section of the pin is disabled ( figure 31 ). [8] if this pin is configured for its vddcmp function, it cannot be used for swclk when the part is on the board. the bypass fil ter of the power supply filters out the swclk clock input signal. [9] 5 v tolerant pin providing standard digita l i/o functions with configurable modes, configurable hysteresis, and analog i/o. when configured as an analog i/o, digital section of the pi n is disabled, and the pin is not 5 v tolerant ( figure 31 ). [10] i 2 c-bus pins are standard digital i/o pins and have limited perform ance and electrical characterist ics compared to the full i 2 c-bus specification. pins can be configured with an on-chip pull-up resistor (pmos device) and with open-drain mode. in this mode, ty pical bit rates of up to 100 kbit/s with 20 pf load are supported if t he internal pull-ups are enabled. higher bit rates can be achieved with an external resistor. [11] when the system oscillator is not used, connect xtalin and xtalout as follows: xtalin can be left floating or can be ground ed (grounding is preferred to reduce susceptibility to noise). xtalout should be left floating. see section 12.3 if an external clock is connected to the xtalin pin. [12] if separate supplies are used for v dd(3v3) and v dd(io) , ensure that the power supply pins are fi ltered for noise with respect to their corresponding grounds v ss and v ss(io) (lqfp48 package). using separate filtered suppl ies reduces the noise to the analog blocks (see also section 12.1 ). [13] if separate supplies are used for v dd(3v3) and v dd(io) , ensure that the voltage difference betw een both supplies is smaller than or equal to 0.5 v. [14] thermal pad (hvqfn33 pin package). connect to ground. v ss(io) 533e3 [14] - - ground. v dd(3v3) 44 29 e2 [12] [13] - - 3.3 v supply voltage to the analog blocks, internal regulator, and internal clock generator circuits. also used as the adc reference voltage. v ss 42 33 e3 [14] - - ground. table 4. lpc11axx pin description table symbol pin/ball type reset state [1] description lqfp48 hvqfn33 wlcsp20
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 23 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller 7. functional description 7.1 arm cortex-m0 processor the arm cortex-m0 is a general purpose, 32-bit microprocessor, which offers high performance and very low power consumption. 7.2 on-chip flash program memory the lpc11axx contain up to 32 kb of on-chip flash program memory. 7.3 on-chip eeprom data memory the lpc11axx contain up to 4 kb of on-chip eeprom data memory. remark: the top 64 bytes of the 4 kb eeprom memory are reserved and cannot be written to. the entire eeprom is writable for smaller eeprom sizes. 7.4 on-chip sram the lpc11axx contain a total of 8 kb, 4 kb, or 2 kb on-chip static ram data memory. 7.5 on-chip rom the on-chip rom contains the boot loader and the following application programming interfaces (api): ? in-system programming (isp) and in-application programming (iap) support for flash programming ? power profiles for configuring po wer consumption and pll settings ? 32-bit integer division routines ? i 2 c-bus driver routines 7.6 memory map the lpc11axx incorporates several distinct memory regions, shown in the following figures. figure 5 shows the overall map of the entire address space from the user program viewpoint following reset. the interrupt vector area supports address remapping. the ahb peripheral area is 2 mb in size, and is divided to allow for up to 128 peripherals. the apb peripheral area is 512 kb in size and is divided to allow fo r up to 32 peripherals. each peripheral of either type is allocated 16 kb of space. this allows simplifying the address decoding for each peripheral.
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 24 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller 7.7 nested vectored inte rrupt controller (nvic) the nested vectored in terrupt controller (nvic) is an integral part of the cortex-m0. the tight coupling to the cpu allows for low interr upt latency and efficient processing of late arriving interrupts. 7.7.1 features ? controls system exceptions and peripheral interrupts. ? in the lpc11axx, the nvic supports 32 vectored interrupts including up to 8 inputs to the start logic from the individual gpio pins. fig 5. lpc11axx memory map apb peripherals 0x4000 4000 0x4000 8000 0x4000 c000 0x4001 0000 0x4001 8000 0x4002 0000 0x4002 8000 0x4003 8000 0x4003 c000 0x4004 0000 0x4004 4000 0x4004 8000 0x4004 c000 0x4005 8000 0x4005 c000 0x4008 0000 0x4002 4000 0x4001 c000 0x4001 4000 0x4000 0000 wwdt 32-bit counter/timer 0 32-bit counter/timer 1 adc usart i 2 c-bus 11 - 13 reserved dac ssp0 ssp1 reserved gpio interrupts reserved reserved reserved 25 - 31 reserved 0 1 2 3 4 5 6 7 8 9 0x4002 c000 analog comparator 10 16 15 14 17 18 reserved reserved 0x0000 0000 0 gb 0.5 gb 4 gb 1 gb 0x1000 1800 0x1000 1000 0x1000 0800 0x1fff 0000 0x1fff 4000 0x2000 0000 0x4000 0000 0x4008 0000 0x5000 0000 0x5004 0000 0xffff ffff reserved reserved reserved apb peripherals gpio 0x1000 0000 2 kb sram (lpc11ax/001) 4 kb sram (lpc11ax/101, lpc11a02)) 6 kb sram (lpc11a1x/201) 0x1000 2000 8 kb sram (lpc11a1x/301, lpc11a04) lpc11axx 16 kb boot rom 0x0000 0000 0x0000 00c0 active interrupt vectors 002aaf429 reserved reserved 16-bit counter/timer 1 16-bit counter/timer 0 ioconfig system control 0x4005 0000 0x4005 4000 22 gpio group0 int 23 gpio group1 int 24 21 19 20 flash/eeprom controller 0x0000 2000 8 kb on-chip flash (lpc11a11) 0x0000 4000 0x0000 6000 16 kb on-chip flash (lpc11a12, lpc11a02) 0x0000 8000 32 kb on-chip flash (lpc11a14, lpc11a04) 24 kb on-chip flash (lpc11a13) 0xe000 0000 0xe010 0000 private peripheral bus
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 25 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller ? four programmable interrupt priority levels with hardware priority level masking. ? software interr upt generation. 7.7.2 interrupt sources each peripheral device has one interrupt line connected to the nvic but may have several interrupt flags. individual interrupt flags may also represent more than one interrupt source. up to eight gpio pins, regardless of t he selected function, can be programmed to generate an interrupt on a le vel, or rising edge or fallin g edge, or both. the interrupt generating gpios can be selected from the gpio pins with a configurable input glitch filter. 7.8 iocon block the iocon block allows selected pins of the microcontroller to have more than one function. configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals. peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt(s) being enabled. activi ty of any enabled peripheral function that is not mapped to a related pin should be considered undefined. up to 16 pins can be configured with a digital input glitch filter for removing voltage glitches with widths of 10 ns or less (see ta b l e 3 and table 4 ), two pins (pio0_2 and pio0_3) can be configured with a 50 ns digital input glitch filter. 7.9 fast general purpose parallel i/o device pins that are not connec ted to a specific peripheral function are controlled by the gpio registers. pins may be dynamically configured as inputs or outputs. multiple outputs can be set or cleared in one write operation. lpc11axx use accelerated gpio functions: ? gpio registers are a dedicated ahb peripheral so that the fastest possible i/o timing can be achieved. ? an entire port value can be written in one instruction. additionally, any gpio pin (total of up to 42 pins) providing a digital function can be programmed to generate an interrupt on a level, a rising or falling edge, or both. 7.9.1 features ? bit level port registers allow a single instruction to set and clear any number of bits in one write operation. ? direction control of individual bits. ? all i/o default to inputs with internal pull-up resistors enabled after reset - except for the i 2 c-bus true open-drain pins pio0_2 and pio0_3. ? pull-up/pull-down configuration, repeater, and open-drain modes can be programmed through the iocon block for each gpio pin (see figure 31 and figure 32 for functional diagrams).
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 26 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller ? control of the digital output slew rate allo wing to switch more ou tputs simultaneously without degrading the power/gro und distribution of the device. 7.10 usart the lpc11axx contains one usart. support for rs-485/9-bit mode allows both software address detection and automatic address detection using 9-bit mode. the usart includes a fractional baud rate generator. standard baud rates such as 115200 bd can be achieved with any crystal frequency above 2 mhz. 7.10.1 features ? maximum usart data bit rate of 3.125 mbit/s. ? 16-byte receive and transmit fifos. ? register locations conform to 16c550 industry standard. ? receiver fifo trigger points at 1 b, 4 b, 8 b, and 14 b. ? built-in fractional baud rate generator cove ring wide range of baud rates without a need for external crystals of particular values. ? fifo control mechanism that enables software flow control implementation. ? support for rs-485/9-bit mode. ? supports a full modem control handshake interface. ? support for synchronous mode. 7.11 ssp serial i/o controller the lpc11axx contain two ssp controllers. the ssp controller is capable of operation on a spi, 4-wire ssi, or microwire bus. it can interact with multiple masters and slaves on the bus. only a single master and a single slave can communicate on the bus during a given data trans fer. the ssp supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. in practice, often only one of these data flows carries meaningful data. 7.11.1 features ? maximum ssp speed of 25 mbit/s (master) or 4.17 mbit/s (s lave) (in spi mode) ? compatible with motorola spi, 4-wire texas instruments ssi, and national semiconductor microwire buses ? synchronous serial communication ? master or slave operation ? 8-frame fifos for both transmit and receive ? 4-bit to 16-bit frame 7.12 i 2 c-bus serial i/o controller the lpc11axx contains one i 2 c-bus controller.
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 27 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller the i 2 c-bus is bidirectional for inter-ic contro l using only two wires: a serial clock line (scl) and a serial data line (sda). each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an lcd driver) or a transmitter with the capability to both receive and send information (such as me mory). transmitters and/or receivers can operate in either master or sl ave mode, depending on whether the chip has to initiate a data transfer or is only addressed. the i 2 c is a multi-master bus and can be controlled by more than one bus master connected to it. remark: on the wlcsp package, the bootloader configures the open-drain pins (pio0_2 and pio0_3) for the serial wire debug (swd) function. 7.12.1 features ? the i 2 c-interface is a standard i 2 c-bus compliant interfac e with open-drain pins (pio0_2 and pio0_3). the i 2 c-bus interface also supports fast-mode plus with bit rates up to 1 mbit/s. for the i 2 c-bus specification, see um10204 . ? the true open-drain pins pio0_2 and pio0_3 can be configured with a 50 ns digital input glitch filter. ? if the true open-drain pins are used for other purposes, a limited-performance i 2 c-bus interface can be configured from a choice of six gpio pins configured in open-drain mode and with a pull-up resistor. in this mode, typical bit rates of up to 100 kbit/s with 20 pf load are supported if the internal pull-ups are enabled. higher bit rates can be achieved with an external resistor. ? fail-safe operation: when the power to an i 2 c-bus device is switched off, the sda and scl pins connected to the i 2 c-bus are floating and do not disturb the bus. ? easy to configure as master, slave, or master/slave. ? rom-based i 2 c-bus driver routines to easily create applications. ? programmable clocks allow versatile rate control. ? bidirectional data transfer between masters and slaves. ? multi-master bus (no central master). ? arbitration between simultaneously transmit ting masters without corruption of serial data on the bus. ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus. ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. ? the i 2 c-bus can be used for test and diagnostic purposes. ? the i 2 c-bus controller supports multiple address recognition and a bus monitor mode. 7.13 configurable analog/ mixed-signal subsystems multiple analog/mixed-signal subsystems can be configured by software from interconnected digital and analog peripherals. see figure 6 .
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 28 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller 7.14 10-bit adc the lpc11axx contains one adc. it is a si ngle 10-bit successive approximation adc with eight channels. fig 6. configurable analog/mixed signal subsystem aaa-003042 10-bit adc 10-bit dac aout acmp_o trig 32-bit timer interrupt controller voltage divider ref signal legend: configurable analog/mixed-signal subsystem ad[7:0] atrg[1:0] vdd(3v3) vddcmp acmp_i[5:1] analog analog comparator arm cortex-m0 digital 0.9 v voltage reference temperature sensor trig mat cap 16-bit timer edge detect mat cap
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 29 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller 7.14.1 features ? 10-bit successive approximation adc. ? input multiplexing among 8 pins. ? power-down mode. ? measurement range 0 v to v dd(3v3) . ? 10-bit conversion time ? 2.44 ? s (up to 400 ksamples/s). ? burst conversion mode for single or multiple inputs. ? optional conversion on transition of input pins atrg0 or atrg1, timer match signal, or comparator output. (input signals must be held for a minimum of three system clock periods). also see section 12.2 . ? individual result registers for each adc channel to reduce interrupt overhead. 7.15 internal voltage reference the internal voltage reference is an accurate 0.9 v and is the output of a low voltage band gap circuit. a typical value at t amb = 25 ? c is 0.903 v and varies typically only ? 3 mv over the 0 ? c to 85 ? c temperature range (see ta b l e 2 1 and figure 27 ). the internal voltage reference can be used in the following applications: fig 7. adc block diagram input mux 10-bit adc aaa-003043 to comparator ad7 ioconfig ioconfig ioconfig ad5 ad6 ad0 adc control register internal voltage reference temperature sensor to comparator ioconfig sensor adc
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 30 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller ? when the supply voltage v dd(3v3) is known accurately, the internal voltage reference can be used to reduce the offset error e o of the adc code output. the adc error correction then increases the accuracy of temperature sensor voltage output measurements. ? when the adc is accurately calibrated, the internal voltage reference can be used to measure the power supply voltage. this requires calibration by recording the adc code of the internal voltage reference at different power supply levels yielding a different adc code value for each supply voltage level. in a particular application, the internal voltage reference can be measured and the actual power supply voltage can be determined from the stored calibration values. the calibration values can be stored in the eeprom for easy access. after power-up and after switching the input channels of the adc or the comparator, the internal voltage reference must be allowed to settle to its stable va lue before it can be used as an adc reference voltage input. settling times are given in ta b l e 2 1 . for an accurate measurement of the internal voltage reference by the adc, the adc must be configured in single-channel burst mode. the last value of a nine-conversion (or more) burst provides an accurate result. 7.16 temperature sensor the temperature sensor transducer uses an intrinsic pn-junction diode reference and outputs a ctat voltage (complement to absolute temperature). the output voltage varies inversely with device temperature with an absolute accuracy of better than ? 3 ? c over the full temperature range ( ? 40 ? c to +85 ? c). the temperature sensor is only approximately linear with a slight curvature. the output voltage is measured over different ranges of temperatures and fit with linear-least-square lines. see ta b l e 2 3 and figure 28 . for a voltage to temperature conversion, the temperature for a given voltage is calculated using the parameters of the linear-least-square line (see table 23 ). after power-up and after switching the input channels of the adc or the comparator, the temperature sensor output must be allowed to settle to its stable value before it can be used as an accurate adc inpu t. settling times are given in ta b l e 2 2 . for an accurate measurement of the temper ature sensor by the adc, the adc must be configured in single-channel burst mode. the last value of a nine-conversion (or more) burst provides an accurate result. 7.17 10-bit dac the dac allows generation of a variable, rail-to-rail analog output.
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 31 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller 7.17.1 features ? 10-bit dac. ? resistor string architecture. ? buffered output. ? power-down mode. ? conversion speed controlled via a programmable bias current. ? optional output update modes: ? write operations to the dac register. ? a transition of pins atrg0 or atrg1. input signals must be held for a minimum of three system clock periods. ? a timer match signal. ? a comparator output signal held for a minimum of two system clock periods. ? holds output value during sleep mode if the dac is not powered down. 7.18 analog comparator the analog comparator with selectable hysteres is can compare voltage levels on external pins and internal voltages. see ta b l e 2 4 . after power-up and after switching the input chan nels of the comparator , the output of the voltage ladder must be allowed to settle to its stable value before it can be used as a comparator reference input. settling times are given in ta b l e 2 5 . fig 8. dac block diagram 10 10 dac input register d/a converter control and data register apb registers analog comparator output atrg1 atrg0 ct16b1_mat1 ct16b1_mat0 ct32b1_mat1 ct32b1_mat0 aout aaa-003044
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 32 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller 7.18.1 features ? selectable 0 mv, 10 mv ( ? 5 mv), and 20 mv ( ? 10 mv), 40 mv ( ? 20 mv) input hysteresis. ? five selectable external voltages; fully configurable on either positive or negative input channel. ? internal voltage reference from band gap and temperature sensor selectable on either positive or negative input channel. ? 32-stage voltage ladder with the internal reference voltage selectable on either the positive or the negative input channel. see ta b l e 2 4 to ta b l e 2 6 . ? voltage ladder source voltage is selectable from an external pin or the main 3.3 v supply voltage rail. ? voltage ladder can be separa tely powered down for applic ations only requiring the comparator function. ? interrupt outp ut is connected to nvic. ? comparator level output is c onnected to output pin acmp_o. ? comparator output is internally connect ed to the adc and dac and can be used to trigger a conversion. ? the comparator output is also connected in ternally to capture channel 3 on each of the 32-bit and 16-bit counter/timers. fig 9. comparator block diagram 5 32 5 acmpi[5:1] v dd vddcmp internal voltage reference edge detect sync comparator level to adc and dac comparator edge comparator analog block comparator digital block aaa-003045 temperature sensor
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 33 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller 7.19 general purpose externa l event counter/timers the lpc11axx includes two 32-bit counter/ timers and two 16-bit counter/timers. the counter/timer is designed to count cycles of the system derived clock. it can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. each counter/timer also includes four capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. 7.19.1 features ? a 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler. ? counter or timer operation. ? four capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. a capture event may also generate an interrupt. up to three capture channels are pinned out. one channel is internally connected to the comparator output acmp_o. ? four match registers per timer that allow: ? continuous operation with optional interrupt generation on match. ? stop timer on match with optional interrupt generation. ? reset timer on match with optional interrupt generation. ? up to four external outputs corresponding to match registers, with the following capabilities: ? set low on match. ? set high on match. ? toggle on match. ? do nothing on match. 7.20 system tick timer the arm cortex-m0 includes a system tick timer (systic k) that is inte nded to generate a dedicated systick exception at a fi xed time interval (typically 10 ms). 7.21 windowed watc hdog timer (wwdt) the purpose of the watchdog is to reset the controller if software fails to periodically service it within a programmable time window. 7.21.1 features ? internally resets chip if not periodically reloaded during the programmable time-out period. ? optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable. ? optional warning interrupt can be generated at a programmable time prior to watchdog time-out. ? enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. ? incorrect feed sequence causes reset or interrupt if enabled.
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 34 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller ? flag to indicate watchdog reset. ? programmable 24-bit timer with internal prescaler. ? selectable time period from (t cy(wdclk) ? 256 ? 4) to (t cy(wdclk) ? 2 24 ? 4) in multiples of t cy(wdclk) ? 4. ? the watchdog clock (wdclk) source can be se lected from the inte rnal rc oscillator (irc), or the dedicated watchdog oscilla tor (wdosc). this gives a wide range of potential timing choices of watchdog oper ation under different power conditions. 7.22 clocking and power control 7.22.1 crystal and internal oscillators the lpc11axx include four independent oscillators. 1. the crystal oscillator (syso sc) operating at frequencie s between 1 mhz and 25 mhz. 2. the internal rc oscillator (irc) with a fi xed frequency of 12 mhz, trimmed to 1% accuracy. 3. the internal low-power, low-frequency oscillator (lfosc) with a programmable nominal frequency between 9.4 kh z and 2.3 mhz with 40% accuracy. 4. the dedicated watchdog oscillator (w dosc) with a programmable nominal frequency between 9.4 khz and 2.3 mhz with 40% accuracy. each oscillator, except the wdosc, can be used for more than one purpose as required in a particular application. following reset, the lpc11axx will operate from the irc until switched by software. this allows systems to operate without any external crystal and the bootloader code to operate at a known frequency. see figure 10 for an overview of the lpc11axx clock generation.
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 35 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller 7.22.1.1 internal rc oscillator (irc) the irc may be used as the clock source for the wwdt, and/or as the clock that drives the pll and subsequently the cpu. the nomi nal irc frequency is 12 mhz. the irc is trimmed to 1 % accuracy over the entire voltage and temperature range. the irc can be used as a clock source fo r the cpu with or without using the pll. the irc frequency can be boosted to a higher frequency, up to the maximum cpu operating frequency, by the system pll. upon power-up or any chip reset, the lpc11axx use the irc as the clock source. software may later switch to one of the other available clock sources. 7.22.1.2 crystal oscillator (sysosc) the crystal oscillator can be used as the clo ck source for the cpu, with or without using the pll. the sysosc operates at frequencies of 1 mhz to 25 mhz. this frequency can be boosted to a higher frequency, up to the maximum cpu operating frequency, by the system pll. fig 10. lpc11axx clock generation block diagram system pll irc sysosc wdosc irc lfosc mainclksel (main clock select) syspllclksel (system pll clock select) system clock divider system sysclkctrl[1:18] memories and peripherals ssp0 peripheral clock divider ssp0 ssp1 peripheral clock divider ssp1 usart peripheral clock divider usart wwdt clock divider wwdt wdclksel lfosc irc sysosc clkout pin clock divider clkout pin clkoutuen (clkout update enable) 002aaf430 main clock system clock irc 18 clkin
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 36 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller 7.22.1.3 internal low-frequency oscillator (lfosc) and watchdog oscillator (wdosc) the lfosc and the wdosc are identical inter nal oscillators. the nom inal frequency is programmable betwee n 9.4 khz and 2.3 mhz. the frequency spread over silicon process variations is ? 40%. the wdosc is a dedicated oscillator for the windowed wwdt. the lfosc can be used as a clock source that directly drives th e cpu or the clkout pin. 7.22.2 clock input a 3.3 v external clock source (25 mhz typical) can be supplied on the selected clkin pin or a 1.8 v external clock source can be supplied on the xtalin pin (see section 12.3 ). 7.22.3 system pll the pll accepts an input clock frequency in the range of 10 mhz to 25 mhz. the input frequency is multiplied up to a high frequency with a curren t controlled oscillator (cco). the multiplier can be an integer value from 1 to 32. the cco operates in the range of 156 mhz to 320 mhz, so there is an additional divider in the loop to keep the cco within its frequency range while the pll is provid ing the desired output frequency. the output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. since the minimum output divider value is 2, it is insu red that the pll output has a 50 % duty cycle. the pll is turned off and bypassed following a chip reset and may be enabled by software. the program must configure and activate the pll, wait for the pll to lock, and then connect to the pll as a clock source. the pll settling time is 100 ? s. 7.22.4 clock output the lpc11axx features a cloc k output function that rout es the irc, the sysosc, the lfosc, or the main clock to an output pin. 7.22.5 wake-up process the lpc11axx begin operation at power-up by using the irc as the clock source. this allows chip operation to resume quickly. if th e sysosc, the external clock source, or the pll is needed by the app lication, software will need to ena ble these features and wait for them to stabilize before they are used as a clock source. 7.22.6 power control the lpc11axx supports the arm cortex-m0 sleep mode. the cpu clock rate may also be controlled as needed by changing clock sources, reconfiguring pll values, and/or altering the cpu clock divider value. this a llows a trade-off of power versus processing speed based on application requirements. in addition, a register is provided for shutting down the clocks to individual on-chip pe ripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. selected peripherals have their own clock divider which provides even better power control. 7.22.6.1 sleep mode when sleep mode is entered, the clock to the core is stopped. resumption from the sleep mode does not need any special sequence but re-enabling the clock to the arm core.
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 37 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller in sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. peripheral functions continue opera tion during sleep mode and may generate interrupts to cause the processor to resume execution. sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. 7.22.6.2 power profiles the power consumption in active and sleep modes can be optimized for the application through simple calls to the power profile. the power configuration routine configures the lpc11axx for one of the following power modes: ? default mode corresponding to power configuration after reset. ? cpu performance mode co rresponding to optimize d processing capability. ? efficiency mode corresponding to optimize d balance of current consumption and cpu performance. ? low-current mode corresponding to lowest power consumption. in addition, the power profile includes routines to select the optimal pll settings for a given system clock and pll input clock. 7.23 system control 7.23.1 undervoltage lockout (uvlo) protection the bod and por circuits remain enabled at all times to provide uvlo protection from an unexpected power supply droop below a typical threshold level of 2.4 v (see also the lpc11axx user manual ). uvlo protection means that the lpc11axx is held in reset whenever the supply voltage falls below 2.4 v. see also section 10.1 ? power supply fluctuations ? , section 12.7 ? uvlo protection and reset timer circuit ? , and section 12.8 ? guidelines for selecting a power supply filter for uvlo protection ? . 7.23.2 reset reset has several sources on the lpc11axx: the reset pin, the watchdog reset, power-on reset (por), the arm sysresetre q software request, and the brown-out detection (bod) circuit. after the bod and the por resets are released, the internal reset timer counts for 100 s until the internal reset is removed. assertion of chip reset by any source (after the operating voltage attains a usable level) starts the irc and initializes the flash memory controller. when the internal reset is removed, the proc essor begins executing at address 0, which is initially the reset vector mapped from the bo ot block. at that point, all of the processor and peripheral registers have been in itialized to predetermined values. writing to a special function re gister allows the software to reset the following peripherals: the i 2 c-bus interface, the usart, both ssp controllers, the four counter/timers, the comparator, the adc, and the dac. the reset pin is a schmitt trigger input pin and uses a special pad. see figure 32 .
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 38 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller 7.23.3 brown-out detection the lpc11axx include two programmable levels for monitoring the voltage on the v dd(3v3) pin. if this voltage falls below the sele cted level, the bod asserts an interrupt signal to the nvic. this signal can be enabled for interrupt in the interrupt enable register in the nvic in order to cause a cpu interrupt; alternatively, software can monitor the signal by reading a dedicated status regist er. in addition, the bod circuit supports one hardware controlled voltage leve l for triggering a chip reset. 7.23.4 code security (code read protection - crp) this feature of the lpc11axx allows user to enable different levels of security in the system so that access to the on-chip flash and use of the serial wire debugger (swd) and in-system-programming (isp) can be re stricted. when needed, crp is invoked by programming a specific pattern into a ded icated flash location. iap commands are not affected by the crp. in addition, isp entry via the pio0_1 pin can be disabled without enabling crp. for details see the lpc11axx user manual . there are three levels of code read protection: 1. crp1 disables access to the chip via the swd and allows partial flash update (excluding flash sector 0) using a limited set of the isp commands. this mode is useful when crp is required and flash fi eld updates are needed but all sectors can not be erased. 2. crp2 disables access to the chip via the swd and only allows full flash erase and update using a reduced set of the isp commands. 3. running an application with level crp3 select ed fully disables any access to the chip via the swd pins and the isp. this mode effectively disables isp override using pio0_1 pin, too. it is up to the user?s application to provide (if needed) flash update mechanism using iap calls or call reinvoke isp command to enable flash update via the usart. in addition to the three crp levels, sampli ng of pin pio0_1 for valid user code can be disabled. for details see the lpc11axx user manual . 7.23.5 apb interface the apb peripherals are located on one apb bus. 7.23.6 ahblite the ahblite connects the cpu bus of the arm cortex-m0 to the flash memory, the main static ram, and the boot rom. caution if level three code read protection (crp3) is selected, no future factory testing can be performed on the device.
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 39 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller 7.23.7 external interrupt inputs all gpio pins can be level or edge sensitive interrupt inputs. 7.24 emulation and debugging debug functions are integrated into the arm cortex-m0. jtag and serial wire debug (swd) with four breakpoints and two watchpoints are supported. the reset pin selects between the jtag boundary scan (reset = low) and the arm swd debug (reset = high). the arm swd debug port is disabled while the lpc11axx is in reset. to perform boundary scan testing, follow these steps: 1. erase any user code residing in flash. 2. power up the part with the reset pin pulled high externally. 3. wait for at least 250 ? s. 4. pull the reset pin low externally. 5. perform boundary scan operations. 6. once the boundary scan operations are completed, assert the trst pin to enable the swd debug mode and release the reset pin (pull high). remark: the jtag interface cannot be used for debug purposes. on the wlcsp package, the tck signal is shared with the vddcmp input on pin pio0_5. to perform a boundary scan on a blan k device, make sure that the pio0_5 pin is not filtered on the board. the bypass filter usually added to the comparator voltage reference input (vddcmp) filters out the swclk/tck input signal. for swd debug, an alternative tck/swclk cloc k pin is available on pin pio0_2. this is the default function after booting for the wlcsp package.
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 40 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller 8. limiting values [1] the following applies to the limiting values: a) this product includes circuitry specif ically designed for the protection of its in ternal devices from the damaging effects of excessive static charge. nonetheless, it is sugges ted that conventional precautions be tak en to avoid applying greater than the rated maximum. b) parameters are valid over operating te mperature range unless otherwise specifi ed. all voltages are with respect to v ss unless otherwise noted. [2] maximum/minimum voltage above the maximum operating voltage (see table 6 ) and below ground that can be applied for a short time (< 10 ms) to a device without leading to irrecoverable failure. failure includes the loss of reli ability and shorter lifetime o f the device. [3] applies to all 5 v tolerant i/o pins except true open-drain pi ns pio0_2 and pio0_3 and except the 3 v tolerant pins pio0_4 a nd pio0_14 (lqfp and hvqfn packages) or pio0_5 (wlcsp package). table 5. limiting values in accordance with the absolute ma ximum rating system (iec 60134). [1] symbol parameter conditions min max unit v dd(3v3) supply voltage (3.3 v) [2] ? 0.5 4.6 v v dd(io) input/output supply voltage [2] ? 0.5 4.6 v v i input voltage 5 v tolerant i/o pins; only valid when the v dd(io) supply voltage is present [3] [4] ? 0.5 +5.5 v on pins pio0_2 and pio0_3 [5] ? 0.5 +5.5 v 3 v tolerant i/o pins without over-voltage protection [6] ? 0.5 +3.6 v v ia analog input voltage [7] [8] [9] ? 0.5 v 4.6 v v i(xtal) crystal input voltage [2] ? 0.5 +2.5 v i dd supply current per supply pin - 100 ma i ss ground current per ground pin - 100 ma i latch i/o latch-up current ? (0.5v dd(io) ) < v i < (1.5v dd(io) ); t j < 125 ? c - 100 ma t stg storage temperature [10] ? 65 +150 ?c t j(max) maximum junction temperature - 150 ?c p tot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption -1 . 5w v esd electrostatic discharge voltage human body model; all pins [11] ? 6.5 +6.5 kv v trig trigger voltage for lvtscr based esd pin protection; 1 ns to 10 ns rise time [12] 8.2 - v ? 10 ns rise time ? 8.5 - v
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 41 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller [4] including the voltage on outputs in 3-state mode. [5] v dd(io) present or not present. compliant with the i 2 c-bus standard. 5.5 v can be applied to this pin when v dd(io) is powered down. [6] applies to 3 v tolerant pins pio0_4 and pio0_14 (lqfp and hvqfn packages) or pio0_5 (wlcsp package). [7] an adc input voltage above 3.6 v can be applied for a short ti me without leading to immediate, unrecoverable failure. accumu lated exposure to elevated voltages at 4.6 v must be less than 10 6 s total over the lifetime of the device. applying an elevated voltage to the adc inputs for a long time affects the reliabili ty of the device and reduces its lifetime. [8] if the comparator is configured with the common mode input v ic = v dd , the other comparator input can be up to 0.2 v above or below v dd without affecting the hysteresis range of the comparator function. [9] it is recommended to connect an overvoltage protection diode between the analog input pin and the voltage supply pin. [10] dependent on package type. [11] human body model: equivalent to dischar ging a 100 pf capacitor through a 1.5 k ? series resistor. [12] not characterized.
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 42 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller 9. static characteristics table 6. static characteristics t amb = ? 40 ? c to +85 ? c, unless otherwise specified. symbol parameter conditions min typ [1] max unit v dd(3v3) supply voltage (3.3 v) 2.6 3.3 3.6 v v dd(io) input/output supply voltage 2.6 3.3 3.6 v i dd supply current active mode; code while(1){} executed from flash; v dd(3v3) = v dd(io) = 3.3 v; low-current mode (see section 7.22.6.2 ) system clock = 12 mhz; all peripherals disabled [2] [4] [5] -3-m a system clock = 48 mhz; all peripherals disabled [2] [6] [5] -8-m a sleep mode; system clock = 12 mhz; v dd(3v3) = v dd(io) = 3.3 v; low-current mode (see section 7.22.6.2 ) all peripherals disabled; 12 mhz [2] [4] [5] -2-m a all peripherals disabled; 48 mhz [2] [4] [5] -5-m a standard port pins, reset i il low-level input current v i = 0 v; on-chip pull-up resistor disabled - 0.5 1000 na i ih high-level input current v i =v dd(io) ; on-chip pull-down resistor disabled - 0.5 1000 na i oz off-state output current v o =0v; v o =v dd(io) ; on-chip pull-up/down resistors disabled - 0.5 1000 na v i input voltage pin configured to provide a digital function 5 v tolerant pins [7] [8] 0- 5 . 0v 3 v tolerant pins: pio0_4 and pio0_14 (lqfp and hvqfn packages) or pio0_5 (hvqfn package) [7] [8] v dd(io) v o output voltage output active 0 - v dd(io) v v ih high-level input voltage 0.7v dd(io) --v v il low-level input voltage - - 0.3v dd(io) v v hys hysteresis voltage 3.0 v ? v dd(io) ?? 3.6 v 0.4 - - v
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 43 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller v oh high-level output voltage 2.6 v ? v dd(io) ?? 3.6 v; i oh = ? 4 ma 0.85v dd(io) --v v ol low-level output voltage 2.6 v ? v dd(io) ?? 3.6 v; i ol =4 ma --0.15v dd(io) v i oh high-level output current v oh =v dd(io) ? 0.4 v; 2.6 v ? v dd(io) ?? 3.6 v ? 4--ma i ol low-level output current v ol =0.4v 2.6 v ? v dd(io) ?? 3.6 v 4--m a i ohs high-level short-circuit output current v oh =0v [9] --? 45 ma i ols low-level short-circuit output current v ol =v dd(io) [9] --5 0m a i pd pull-down current v i =5v [10] 10 50 150 ? a i pu pull-up current v i =0v; 2.6 v ? v dd(io) ?? 3.6 v ? 15 ? 50 ? 85 ? a v dd(io) lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 44 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller [1] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [2] t amb =25 ? c. [3] i dd measurements were performed with all pins configured as gpio outputs driven low and pull-up resistors disabled. [4] irc enabled; sysosc disabled; system pll disabled. [5] all digital peripherals disabled in the sysclkctrl register except rom, ram, and flash. peripheral clocks to usart and ssp0/ 1 disabled in system configuration block. analog peripherals disabled in the p druncfg register except flash memory. [6] irc disabled; sysosc enabled; system pll enabled. [7] including voltage on outputs in 3-state mode. [8] all supply voltages must be present. [9] allowed as long as the current limit does not exceed the maximum current allowed by the device. [10] does not apply to 3 v tolerant pins pio0_4 and pi o0_14 (lqfp and hvqfn packages) or pio0_5 (hvqfn package). [11] to v ss . i ohs high-level short-circuit output current v oh =0v [9] --? 160 ma i ols low-level short-circuit output current v ol =v dd(io) [9] --5 0m a i pd pull-down current v i =5v 10 50 150 ? a i pu pull-up current v i =0v 2.6 v ? v dd(io) ?? 3.6 v ? 15 ? 50 ? 85 ? a v dd(io) lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 45 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller 9.1 power consumption power measurements in active and sleep modes were performed under the following conditions (see lpc11axx user manual ): ? configure all pins as gpio with pull-up resistor disabled in the iocon block. ? configure gpio pins as outputs using the gpiondir registers. ? write 0 to all gpio dir registers to drive the outputs low. conditions: v dd(3v3) = 3.3 v; active mode entered executing code while(1){} from flash; all peripherals disabled in the sysahbclkctrl register; all peripheral clocks disabled; all analog peripherals disabled in the pdruncfg register; low-current mode (see section 7.22.6.2 ). (1) sysosc and system pll disabled; irc enabled. (2) sysosc and system pll enabled; irc disabled. fig 11. active mode: typical supply current i dd versus temperature for different system clock frequencies (all peripherals disabled) 002aah184 -40 -15 10 35 60 85 0 1.6 3.2 4.8 6.4 8 temperature (c) i dd (ma) 12 mhz (1) 24 mhz (2) 36 mhz (2) 48 mhz (2)
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 46 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller conditions: t amb = 25 c; active mode entered executing code while(1){} from flash; all peripherals disabled in the sysahbclkctrl register; all per ipheral clocks disabled; all analog peripherals disabled in the pdruncfg register; low-current mode (see section 7.22.6.2 ). (1) sysosc and system pll disabled; irc enabled. (2) sysosc and system pll enabled; irc disabled. fig 12. active mode: typical supply current i dd versus core voltage v dd(3v3) for different system clock frequencies (all peripherals disabled) conditions: v dd(3v3) = 3.3 v; sleep mode entered from flash; all peripherals disabled in the sysahbclkctrl register and pdruncfg register ; all peripheral cloc ks disabled; bod disabled; low-current mode (see section 7.22.6.2 ). (1) sysosc and system pll disabled; irc enabled. (2) sysosc and system pll enabled; irc disabled. fig 13. sleep mode: typical supply current i dd versus temperature for different system clock frequencies (all peripherals disabled) 002aah185 2.7 3 3.3 3.6 0 1.6 3.2 4.8 6.4 8 v dd(3v3) (v) i dd (ma) 12 mhz (1) 24 mhz (2) 36 mhz (2) 48 mhz (2) 002aah186 -40 -15 10 35 60 85 0 1.6 3.2 4.8 6.4 8 temperature (c) i dd (ma) 12 mhz (1) 24 mhz (2) 36 mhz (2) 48 mhz (2)
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 47 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller 9.2 peripheral power consumption the supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the sysahbclkcfg and pdruncfg (for analog blocks) registers. all other blocks are disabled in both registers and no code is executed. me asured on a typical sample at t amb =25 ? c. [1] irc on; pll off. 9.3 electrical pi n characteristics table 7. power consumption for individual analog and digital blocks peripheral typical supply current in ma 12 mhz [1] average ? a/mhz analog peripherals bod 0.05 - bod, comparator 0.14 - bod, comparator, adc, dac, temperature sensor 0.40 - dac 0.26 - adc 0.01 - temperature sensor, adc 0.01 - digital peripherals usart 0.15 12 i2c 0.02 2 16-bit counter/timer 0/1 0.02 2 32-bit counter/timer 0/1 0.02 2 wwdt 0.02 2 conditions: v dd(io) = 3.3 v; on pin pio0_21. fig 14. high-current source output driver: typical high-level output voltage v oh versus high-level output current i oh i oh (ma) 0 60 40 20 10 50 30 002aae990 2.8 2.4 3.2 3.6 v oh (v) 2 t = 85 c 25 c ?40 c
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 48 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller conditions: v dd(io) = 3.3 v; on pins pio0_2 and pio0_3. fig 15. high-current sink pins: typical low-level output current i ol versus low-level output voltage v ol conditions: v dd(io) = 3.3 v; standard port pins and pio0_21. fig 16. typical low-l evel output current i ol versus low-level output voltage v ol v ol (v) 0 0.6 0.4 0.2 002aaf019 20 40 60 i ol (ma) 0 t = 85 c 25 c ?40 c v ol (v) 0 0.6 0.4 0.2 002aae991 5 10 15 i ol (ma) 0 t = 85 c 25 c ?40 c
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 49 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller conditions: v dd(io) = 3.3 v; standard port pins. fig 17. typical high-level output voltage v oh versus high-level output source current i oh conditions: v dd(io) = 3.3 v; standard port pins. fig 18. typical pull-up current i pu versus input voltage v i i oh (ma) 0 24 16 8 002aae992 2.8 2.4 3.2 3.6 v oh (v) 2 t = 85 c 25 c ?40 c v i (v) 0 5 4 23 1 002aae988 ?30 ?50 ?10 10 i pu (a) ?70 t = 85 c 25 c ?40 c
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 50 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller conditions: v dd(io) = 3.3 v; standard port pins. fig 19. typical pull-down current i pd versus input voltage v i v i (v) 0 5 4 23 1 002aae989 40 20 60 80 i pd (a) 0 t = 85 c 25 c ?40 c
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 51 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller 10. dynamic characteristics 10.1 power supply fluctuations if the input voltage (v dd(3v3) ) to the internal regulator fluctuates, the lpc11axx is held in reset during a brown-out condition as long as the uvlo circuit is operating. the settling times of the bod and por circuits, which co nstitute the uvlo, determine the minimum time the supply level must remain in the shallow or deep brown-out condition to ensure that the internal reset is asserted properly. see also section 7.23.1 , section 12.7 , and section 12.8 . 10.2 flash/eeprom memory table 8. uvlo circuits settling characteristics symbol parameter conditions min typ max unit t s settling time power droop: from active level to shallow brown-out level (0.9 v ? v dd(3v3) ? 2.4 v) 5-- ? s from active level to deep brown-out level (0 < v dd(3v3) < 0.9 v) 12 - - ? s fig 20. uvlo timing external power supply bod trip point (typical) por trip point (typical) internal reset time brown-out shallow brown-out deep supply voltage v dd(3v3) 2.4 v 0.9 v 0 v cold start-up > 5 s > 12 s 002aah326 table 9. flash characteristics t amb = ? 40 ? c to +85 ? c. based on jedec nvm qualification. failure rate < 10 ppm for parts as specified below. symbol parameter conditions min typ max unit n endu endurance [2] [1] 10000 100000 - cycles
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 52 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller [1] number of program/erase cycles. [2] min and max values are valid for t amb = ?40 ? c to +85 ? c only. [3] programming times are given for writing 256 bytes to the flash. t amb < +85 ? c. data must be written to the flash in blocks of 256 bytes. flash progr amming is accomplish ed via iap calls (see lpc11axx user manual ). execution time of iap calls depends on the syst em clock and is typically between 1.5 and 2 ms per 256 bytes. [1] min and max values are valid for t amb = ?40 ? c to +85 ? c only. [2] t amb < +85 ? c. 10.3 external clock for o scillator in slave mode remark: the input voltage on the xtalin pin must be ? 1.95 v (see ta b l e 6 ). for connecting the oscillator to the xtalin/xtalout pins also see section 12.3 . [1] parameters are valid over operating temp erature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. t ret retention time powered [2] 10 20 - years unpowered [2] 20 40 - years t er erase time sector or multiple consecutive sectors [2] 95 100 105 ms t prog programming time [2] [3] 0.95 1 1.05 ms table 10. eeprom characteristics t amb = ? 55 ? cto+125 ? c; v dd(3v3) = 2.7 v to 3.6 v. based on jedec nvm qualification. failure rate < 10 ppm for parts as specified below. symbol parameter conditions min typ max unit n endu endurance [1] 100000 1000000 - cycles t ret retention time powered [1] 100 200 - years unpowered [1] 150 300 - years t prog programming time 64 bytes [2] -1 . 1 -m s table 9. flash characteristics t amb = ? 40 ? c to +85 ? c. based on jedec nvm qualification. failure rate < 10 ppm for parts as specified below. symbol parameter conditions min typ max unit table 11. dynamic characteristic: ext ernal clock (xtalin or clkin pin) t amb = ? 40 ? c to +85 ? c; v dd(3v3) over specified ranges. [1] symbol parameter conditions min typ [2] max unit f osc oscillator frequency 1 - 25 mhz t cy(clk) clock cycle time 40 - 1000 ns t chcx clock high time t cy(clk) ? 0.4--ns t clcx clock low time t cy(clk) ? 0.4--ns t clch clock rise time - - 5 ns t chcl clock fall time - - 5 ns
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 53 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller 10.4 internal oscillators [1] parameters are valid over operating temp erature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [1] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. fig 21. external clock timing (with an amplitude of at least v i(rms) = 200 mv) t chcl t clcx t chcx t cy(clk) t clch 002aaa907 table 12. dynamic characteristic: irc t amb = ? 40 ? c to +85 ? c; 2.7 v ? v dd(3v3) ? 3.6 v. [1] symbol parameter conditions min typ [2] max unit f osc(rc) internal rc oscillator frequency - 11.88 12 12.12 mhz conditions: frequency values are typical values. 12 mhz ? 1% accuracy is guaranteed for 2.7 v ? v dd(3v3) ? 3.6 v and t amb = ?40 ? c to +85 ? c. variations between parts may cause the irc to fall outside the 12 mhz ? 1% accuracy specificatio n for voltages below 2.7 v. fig 22. internal irc frequency vs. temperature table 13. dynamic characteri stics: wdosc and lfosc symbol parameter conditions min typ [1] max unit f osc internal oscillator frequency divsel = 0x1f, freqsel = 0x1 in the wdtoscctrl register; [2] [3] -9.4 - khz divsel = 0x00, freqsel = 0xf in the wdtoscctrl register [2] [3] - 2300 - khz 002aah011 11.95 12.05 12.15 f (mhz) 11.85 temperature (c) -40 85 35 10 60 -15 vdd = 3.6 v 3.3 v 3.0 v 2.7 v
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 54 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller [2] the typical frequency spread over processing and temperature (t amb = ?40 ? c to +85 ? c) is ? 40%. [3] see the lpc11axx user manual. 10.5 i/o pins [1] applies to standard port pins and reset pin. simulated results. [2] sso indicates maximum number of simultaneously swit ching digital output pins. the pins are optimized for half of the maximum sso. [3] set slew bit in the iocon register to 1. [4] set slew bit in the iocon register to 0. 10.6 i 2 c-bus remark: all i 2 c modes (standard-mode, fast-mode, fa st-mode plus) can be configured for the true open-drain pins pio0_2 and pio0_3. if the limited-performance i 2 c-bus pins are used (i 2 c-bus functions on standard i/o pins ), only standard-mode with internal pull-up enabled or fast-mode with external pull-up resistor are supported. table 14. dynamic characte ristic: digital i/o pins [1] t amb = ? 40 ? c to +85 ? c; 3.0 v ? v dd(io) ? 3.6 v; load capacitor = 30 pf. symbol parameter conditions min typ max unit t r rise time pin configured as output sso = 1 [2] [3] 2.5 - 5.0 ns sso = 6 [2] [3] 2.5 - 4.5 ns sso = 16 [2] [4] 3.0 - 5.0 ns t f fall time pin configured as output sso = 1 [2] [3] 2.0 - 4.5 ns sso = 6 [2] [3] 2.0 - 4.5 ns sso = 16 [2] [4] 2.5 - 5.0 ns table 15. dynamic characteristic: i 2 c-bus pins [1] t amb = ? 40 ? c to +85 ? c. [2] symbol parameter conditions min max unit f scl scl clock frequency standard-mode 0 100 khz fast-mode 0 400 khz fast-mode plus 0 1 mhz t f fall time [4] [5] [6] [7] of both sda and scl signals standard-mode - 300 ns fast-mode 20 + 0.1 ? c b 300 ns fast-mode plus - 120 ns t low low period of the scl clock standard-mode 4.7 - ? s fast-mode 1.3 - ? s fast-mode plus 0.5 - ? s
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 55 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller [1] see the i 2 c-bus specification um10204 for details. [2] parameters are valid over operating temp erature range unless otherwise specified. [3] t hd;dat is the data hold time that is measured from the falling edge of scl; applies to data in transmission and the acknowledge. [4] a device must internally provide a hold time of at least 300 ns for the sda signal (with respect to the v ih (min) of the scl signal) to bridge the undefined region of the falling edge of scl. [5] c b = total capacitance of one bus line in pf. [6] the maximum t f for the sda and scl bus lines is specified at 300 ns. the maximum fall time for the sda output stage t f is specified at 250 ns. this allows series protection resistors to be connected in between the sda and the scl pins and the sda/scl bus lines without exceeding the maximum specified t f . [7] in fast-mode plus, fall time is specified the same for both output stage and bus timing. if series resistors are used, designers should allow for this when considering bus timing. [8] the maximum t hd;dat could be 3.45 ? s and 0.9 ? s for standard-mode and fast-mode but must be less than the maximum of t vd;dat or t vd;ack by a transition time (see um10204 ). this maximum must only be met if the device does not stretch the low period (t low ) of the scl signal. if the clock stretches the scl, the data must be valid by the set-up time before it releases the clock. [9] t su;dat is the data set-up time that is measured with respect to the rising edge of scl; applies to data in transmission and the acknowledge. [10] a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system but the requirement t su;dat = 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the lo w period of the scl signal, it must output the next data bit to the sda line t r(max) + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the scl line is released. also the acknowledge timing must meet this set-up time. t high high period of the scl clock standard-mode 4.0 - ? s fast-mode 0.6 - ? s fast-mode plus 0.26 - ? s t hd;dat data hold time [3] [4] [8] standard-mode 0 - ? s fast-mode 0 - ? s fast-mode plus 0 - ? s t su;dat data set-up time [9] [10] standard-mode 250 - ns fast-mode 100 - ns fast-mode plus 50 - ns table 15. dynamic characteristic: i 2 c-bus pins [1] t amb = ? 40 ? c to +85 ? c. [2] symbol parameter conditions min max unit
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 56 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller 10.7 ssp interfaces [1] t cy(clk) = (sspclkdiv ? (1 + scr) ? cpsdvsr) / f main . the clock cycle time deriv ed from the spi bit rate t cy(clk) is a function of the main clock frequency f main , the spi peripheral clock divider (sspclkdiv), the spi scr parameter (specified in the ssp0cr0 register), and the spi cpsdvsr parameter (specified in the spi clock prescale register). [2] t amb = ?40 ? c to 85 ? c. [3] t cy(clk) = 12 ? t cy(pclk) . [4] t amb = 25 ? c; for normal voltage supply range: v dd(io) = vdd(3v3) = 3.3 v. fig 23. i 2 c-bus pins clock timing 002aaf425 t f 70 % 30 % sda t f 70 % 30 % s 70 % 30 % 70 % 30 % t hd;dat scl 1 / f scl 70 % 30 % 70 % 30 % t vd;dat t high t low t su;dat table 16. dynamic ch aracteristics of ssp pins in spi mode 2.6 v <= v dd(3v3) = v dd(io) <= 3.6 v. symbol parameter conditions min typ max unit spi master (in spi mode) t cy(clk) clock cycle time full-duplex mode [1] 50 - - ns when only transmitting [1] [1] 40 ns t ds data set-up time in spi mode [1] [2] 15 - - ns t dh data hold time in spi mode [1] [2] 0-- n s t v(q) data output valid time in spi mode [1] [2] -- 1 0 n s t h(q) data output hold time in spi mode [1] [2] 0-- n s spi slave (in spi mode) t cy(pclk) pclk cycle time 20 - - ns t ds data set-up time in spi mode [3] [4] 0-- n s t dh data hold time in spi mode [3] [4] 3 ? t cy(pclk) + 4 - - ns t v(q) data output valid time in spi mode [3] [4] -- 3 ? t cy(pclk) + 11 ns t h(q) data output hold time in spi mode [3] [4] -- 2 ? t cy(pclk) + 5 ns
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 57 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller pin names sck, miso, and mosi refer to pins for both ssp peripherals, ssp0 and ssp1. fig 24. ssp master timing in spi mode sck (cpol = 0) mosi miso t cy(clk) t clk(h) t clk(l) t ds t dh t v(q) data valid data valid t h(q) sck (cpol = 1) data valid data valid mosi miso t ds t dh data valid data valid t h(q) data valid data valid t v(q) cpha = 1 cpha = 0 002aae829
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 58 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller 11. characteristics of analog peripherals [1] interrupt levels are selected by writing the le vel value to the bod control register bodctrl, see lpc11axx user manual . pin names sck, miso, and mosi refer to pins for both ssp peripherals, ssp0 and ssp1. fig 25. ssp slave timing in spi mode sck (cpol = 0) mosi miso t cy(clk) t clk(h) t clk(l) t ds t dh t v(q) data valid data valid t h(q) sck (cpol = 1) data valid data valid mosi miso t ds t dh t v(q) data valid data valid t h(q) data valid data valid cpha = 1 cpha = 0 002aae830 table 17. bod static characteristics [1] t amb =25 ? c. symbol parameter conditions min typ max unit v th threshold voltage interrupt level 2 assertion - 2.52 - v de-assertion - 2.66 - v interrupt level 3 assertion - 2.80 - v de-assertion - 2.90 - v
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 59 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller [1] the adc is monotonic, there are no missing codes. [2] the differential linearity error (e d ) is the difference between the actual step width and the ideal step width. see figure 26 . [3] the integral non-linearity (e l(adj) ) is the peak difference between the c enter of the steps of the actual and the ideal transfer curve after appropriate adj ustment of gain and offset errors. see figure 26 . [4] the offset error (e o ) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. see figure 26 . [5] the full-scale error voltage or gain error (e g ) is the difference between the straight line fitting the actual transfer curve after removing offset error, and the stra ight line which fits the ideal transfer curve. see figure 26 . [6] the absolute error (e t ) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated adc and the ideal transfer curve. see figure 26 . [7] t amb = 25 ? c; maximum sampling frequency f s = 400 ksamples/s and analog input capacitance c ia = 1pf. [8] input resistance r i depends on the sampling frequency f s : r i = 1 / (f s ? c ia ). table 18. adc static characteristics t amb = ? 40 ? c to +85 ? c unless otherwise specified; adc frequency 4.5 mhz, v dd(3v3) = 2.7 v to 3.6 v; v ss = 0 v. symbol parameter conditions min typ max unit v ia analog input voltage 0 - v dd(3v3) v c ia analog input capacitance - - 4 pf e d differential linearity error [1][2] -- ? 1lsb e l(adj) integral non-linearity [3] -- ? 1.5 lsb e o offset error [4] -- ? 20 mv v err(fs) full-scale error voltage [5] -- ? 20 mv e t absolute error [6] -- ? 4lsb r i input resistance [7][8] --2.5 m ?
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 60 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller [1] measured on typical samples. table 19. dac static and dy namic characteristics v dd(3v3) = 2.7 v to 3.6 v; t amb = ? 40 ? c to +85 ? c unless otherwise specified symbol parameter conditions min typ max unit e d differential linearity error -- ? 1lsb e l(adj) integral non-linearity -- ? 1.5 lsb e o offset error - - 20 mv e g gain error - - 20 mv c l load capacitance - - 200 pf r l load resistance 1 - - k ? r o output resistance [1] -< 40 ? f c(dac) dac conversion frequency -0.41mhz t s settling time - - 1 ? s v o output voltage output voltage range with less than 1 lsb deviation; with minimum r l connected to ground or power supply 0.3 - v dd(3v3) ? 0.3 v with minimum r l connected to ground or power supply 0.175 - v dd(3v3) ? 0.175 v table 20. dac sampling frequency range and power consumption bias bit maximum current dac sampling frequency range 0700 ? a 0 mhz to 1 mhz 1350 ? a 0 mhz to 400 khz
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 61 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller (1) example of an actual transfer curve. (2) the ideal transfer curve. (3) differential linearity error (e d ). (4) integral non-linearity (e l(adj) ). (5) center of a step of the actual transfer curve. fig 26. adc characteristics 002aah327 1023 1022 1021 1020 1019 (2) (1) 1024 1018 1019 1020 1021 1022 1023 7 123456 7 6 5 4 3 2 1 0 1018 (5) (4) (3) 1 lsb (ideal) code out v dd(3v3) - v ss 1024 offset error e o gain error e g offset error e o v ia (lsb ideal ) 1 lsb =
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 62 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller [1] characterized through simulation. [2] characterized on a typical silicon sample. [3] typical values are derived from nominal simulation (v dd(3v3) = 3.3 v; t amb = 27 ? c; nominal process models). maximum values are derived from worst case simulation (v dd(3v3) = 2.6 v; t amb = 85 ? c; slow process models). [4] settling time applies to switching between comparator and adc channels. table 21. internal voltage reference static and dynamic characteristics symbol parameter conditions min typ max unit v o output voltage t amb = ? 40 ? c to +85 ?c [1] 0.855 0.900 0.945 v t amb = 70 ? c to 85 ?c [2] -0.906- v t amb = 50 ?c [2] -0.905- v t amb = 25 ?c [3] 0.893 0.903 0.913 v t amb = 0 ?c [2] -0.902- v t amb = ? 20 ?c [2] -0.899- v t amb = ? 40 ?c [2] -0.896- v t s(pu) power-up settling time to 99% of v o [3] - 155 195 ? s t s(sw) switching settling time to 99% of v o [3] [4] -5075 ? s v dd(3v3) = 3.3 v fig 27. typical internal voltage reference output voltage 002aag063 temperature (c) -40 85 35 10 60 -15 895 905 900 910 v o (mv) 890
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 63 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller [1] absolute temperature accuracy. [2] typical values are derived from nominal simulation (v dd(3v3) = 3.3 v; t amb = 27 ? c; nominal process models). maximum values are derived from worst case simulation (v dd(3v3) = 2.6 v; t amb = 85 ? c; slow process models). [3] settling time applies to switching between comparator and adc channels. table 22. temperature sensor stati c and dynamic characteristics v dd(3v3) = 2.6 v to 3.6 v symbol parameter conditions min typ max unit dt sen sensor temperature accuracy t amb = ? 40 ? c to +85 ?c [1] -- ? 3 ?c e l linearity error t amb = ? 40 ? c to +85 ? c-- ? 1.1 ?c t s(pu) power-up settling time to 99% of temperature sensor output value [2] -81 85 ? s t s(sw) switching settling time to 99% of temperature sensor output value [2] [3] -1.52 ? s table 23. temperature sensor linear-least-square (lls) fit parameters v dd(3v3) = 2.6 v to 3.6 v fit parameter range min typ max unit lls slope t amb = 0 ? c to 85 ?c- ? 2.36 - mv/ ?c t amb = ? 40 ? c to +85 ?c- ? 2.36 - mv/ ?c lls intercept t amb = 0 ? c to 85 ?c - 577 - mv t amb = ? 40 ? c to +85 ? c - 576 - mv v dd(3v3) = 3.3 v; measured on a typical silicon sample. fig 28. typical lls fit of the temperature sensor output voltage temperature (c) -40 85 35 10 60 -15 002aag064 400 600 800 v o (mv) 200 y = -2.366x + 578.34 r 2 = 0.9995
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 64 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller [1] c l = 10 pf; results from measurements on silicon samples ov er process corners and over the full temperature range t amb = -40 ? c to +85 ? c. [2] input hysteresis is relative to the referenc e input channel and is software programmable. table 24. comparator characteristics v dd(3v3) = 3.0 v and t amb = 25 ? c unless noted otherwise. symbol parameter conditions min typ max unit static characteristics i dd supply current - 55 - ? a v ic common-mode input voltage 0 - v dd(3v3) v dv o output voltage variation 0 - v dd(3v3) v v offset offset voltage v ic = 0.1 v - ? 4 to +4.2 - mv v ic = 1.5 v - ? 2-mv v ic = 2.8 v - ? 2.5 mv dynamic characteristics t startup start-up time nominal process - 4 - ? s t pd propagation delay high to low; v dd(3v3) = 3.0 v; v ic = 0.1 v; 50 mv overdrive input [1] - 129 140 ns v ic = 0.1 v; rail-to-rail input [1] - 210 250 ns v ic = 1.5 v; 50 mv overdrive input [1] -112 130 ns v ic = 1.5 v; rail-to-rail input [1] - 127 160 ns v ic = 2.9 v; 50 mv overdrive input [1] - 151 170 ns v ic = 2.9 v; rail-to-rail input [1] -57 70 ns t pd propagation delay low to high; v dd(3v3) = 3.0 v; v ic = 0.1 v; 50 mv overdrive input [1] - 232 240 ns v ic = 0.1 v; rail-to-rail input [1] -58 60 ns v ic = 1.5 v; 50 mv overdrive input [1] - 210 230 ns v ic = 1.5 v; rail-to-rail input [1] - 178 200 ns v ic = 2.9 v; 50 mv overdrive input [1] - 166 190 ns v ic = 2.9 v; rail-to-rail input [1] - 333 550 ns v hys hysteresis voltage positive hysteresis; v dd(3v3) = 3.0 v; v ic = 1.5 v [2] - 5, 10, 20 - mv v hys hysteresis voltage negative hysteresis; v dd(3v3) = 3.0 v; v ic = 1.5 v [2] - 5, 10, 20 - mv r lad ladder resistance - - 1.034 - m ?
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 65 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller [1] maximum values are derived fr om worst case simulation (v dd(3v3) = 2.6 v; t amb = 85 ? c; slow process models). [2] settling time applies to switching between comparator and adc channels. [1] measured over a polyresistor matrix lot with a 2 khz input signal and overdrive < 100 ? v. [2] all peripherals except comparator, temperature sensor, and irc turned off. table 25. comparator voltage ladder dynamic characteristics symbol parameter conditions min typ max unit t s(pu) power-up settling time to 99% of voltage ladder output value [1] -- 30 ? s t s(sw) switching settling time to 99% of voltage ladder output value [1] [2] -- 15 ? s table 26. comparator voltage ladder reference static characteristics v dd(3v3) = 3.3 v; t amb = -40 ? c to + 85 ? c. symbol parameter conditions min typ max [1] unit e v(o) output voltage error internal v dd(3v3) supply decimal code = 00 [2] -00 % decimal code = 08 - 0 ? 0.4 % decimal code = 16 - ? 0.2 ? 0.2 % decimal code = 24 - ? 0.2 ? 0.2 % decimal code = 30 - ? 0.1 ? 0.1 % decimal code = 31 - ? 0.1 ? 0.1 % e v(o) output voltage error external vddcmp supply decimal code = 00 - 0 0 % decimal code = 08 - ? 0.1 ? 0.5 % decimal code = 16 - ? 0.2 ? 0.4 % decimal code = 24 - ? 0.2 ? 0.3 % decimal code = 30 - ? 0.2 ? 0.2 % decimal code = 31 - ? 0.1 ? 0.1 %
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 66 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller 12. application information 12.1 adc usage notes the following guidelines show how to increase the performance of the adc in a noisy environment beyond the adc specifications listed in ta b l e 1 8 : ? the adc input trace must be short and as close as possible to the lpc11axx chip. ? the adc input traces must be shielded from fast switching digital signals and noisy power supply lines. ? because the adc and the digital core share the same power supply, the power supply line must be adequately filtered. ? to improve the adc performance in a very no isy environment, put the device in sleep mode during the adc conversion. 12.2 use of adc input trigger signals for applications that use trigger signals to start conversions and require a precise sample frequency, ensure that the period of the trigger signal is an integral multiple of the period of the adc clock. 12.3 xtal input the input voltage to the on-chip oscillators is limited to 1.8 v. if the oscillator is driven by a clock in slave mode, it is recommended that th e input be coupled through a capacitor with c i = 100 pf. to limit the input voltage to the specified range, choose an additional capacitor to ground c g which attenuates the input voltage by a factor c i /(c i + c g ). in slave mode, a minimum of 200 mv(rms) is needed. in slave mode the input clock signal should be coupled by means of a capacitor of 100 pf ( figure 29 ), with an amplitude between 200 mv (rms) and 1000 mv (rms). this corresponds to a square wave signal with a signal swing of between 280 mv and 1.4 v. the xtalout pin in this configur ation can be left unconnected. external components and models used in oscillation mode are shown in figure 30 and in ta b l e 2 7 and ta b l e 2 8 . since the feedback resistance is integrated on chip, only a crystal and the capacitances c x1 and c x2 need to be connected externally in case of fundamental mode oscillation (the fundamental frequenc y is represen ted by l, c l and fig 29. slave mode operation of the on-chip oscillator lpc1xxx xtalin c i 100 pf c g 002aae788
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 67 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller r s ). capacitance c p in figure 30 represents the parallel package capacitance and should not be larger than 7 pf. parameters f osc , c l , r s and c p are supplied by the crystal manufacturer (see ta b l e 2 7 ). fig 30. oscillator modes and models: oscillation mode of operation and external crystal model used for c x1 /c x2 evaluation table 27. recommended values for c x1 /c x2 in oscillation mode (crystal and external components parameters) low frequency mode fundamental oscillation frequency f osc crystal load capacitance c l maximum crystal series resistance r s external load capacitors c x1 , c x2 1 mhz - 5 mhz 10 pf < 300 ? 18 pf, 18 pf 20 pf < 300 ? 39 pf, 39 pf 30 pf < 300 ? 57 pf, 57 pf 5 mhz - 10 mhz 10 pf < 300 ? 18 pf, 18 pf 20 pf < 200 ? 39 pf, 39 pf 30 pf < 100 ? 57 pf, 57 pf 10 mhz - 15 mhz 10 pf < 160 ? 18 pf, 18 pf 20 pf < 60 ? 39 pf, 39 pf 15 mhz - 20 mhz 10 pf < 80 ? 18 pf, 18 pf table 28. recommended values for c x1 /c x2 in oscillation mode (crystal and external components parameters) high frequency mode fundamental oscillation frequency f osc crystal load capacitance c l maximum crystal series resistance r s external load capacitors c x1 , c x2 15 mhz - 20 mhz 10 pf < 180 ? 18 pf, 18 pf 20 pf < 100 ? 39 pf, 39 pf 20 mhz - 25 mhz 10 pf < 160 ? 18 pf, 18 pf 20 pf < 80 ? 39 pf, 39 pf 002aaf424 lpc1xxx xtalin xtalout c x2 c x1 xtal = c l c p r s l
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 68 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller 12.4 xtal printed circuit boar d (pcb) layout guidelines the crystal should be connected on the pcb as close as poss ible to the oscillator input and output pins of the chip. take care that the load capacitors c x1 ,c x2 , and c x3 in case of third overtone crystal usage have a common ground plane. the external components must also be connected to the ground plain. loops must be made as small as possible in order to keep the noise coupled in via the pcb as small as possible. also parasitics should stay as small as possible. values of c x1 and c x2 should be chosen smaller accordingly to the increase in parasitics of the pcb layout. 12.5 standard i/o pad configuration figure 31 shows the possible pin modes for standard i/o pins with analog input function: ? digital output driver with co nfigurable open-drain output ? digital input: weak pull-up resistor (pmos device) enabled/disabled ? digital input: weak pull-down resistor (nmos device) enabled/disabled ? digital input: repeater mode enabled/disabled ? digital input: input glitch f ilter selectable on 17 pins. ? analog input fig 31. standard i/o pad configuration pin v dd v dd esd v ss esd strong pull-up strong pull-down v dd weak pull-up weak pull-down open-drain enable output enable repeater mode enable pull-up enable pull-down enable select data inverter data output data input select glitch filter analog input select analog input 002aaf695 pin configured as digital output driver pin configured as digital input pin configured as analog input 10 ns rc glitch filter
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 69 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller 12.6 reset pad configuration 12.7 uvlo protection and reset timer circuit 12.8 guidelines for selecting a power s upply filter for uvlo protection for the uvlo circuits to hold the part in reset during shallow and deep brown-out conditions, you must filter the power supply line to allow for the bod and por circuits to settle when short voltage drops occur (see section 10.1 ? power supply fluctuations ? ). select the capacitance of the decoupling/by pass capacitor according to the following guidelines: c >> i dd ? t s / ? v dd(3v3) with ? ? v dd(3v3) ? 100 mv for the voltage drop below the bod or por trip points. ? i dd ? 3 ma with the irc running and pll/sysosc off (see figure 12 ). fig 32. reset pad configuration v ss reset 002aaf274 v dd v dd v dd r pu esd esd 20 ns rc glitch filter pin fig 33. functional diagram of the uvlo protection and reset timer circuit 002aah324 internal regulator v int 1.8 v v ext v int v int analog reset v ref por v ext 3.3 v uvlo bod por or or internal reset 100 s reset timer
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 70 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller ? t s = 5 ? s for shallow brown-out (see ta b l e 8 ). ? t s = 12 ? s for deep brown-out (see ta b l e 8 ). with these parameters, the decoupling/bypass capacitor to add to the supply line is: ? c ??? 0.15 ? f for shallow brown-out ? c >> 0.36 ? f for deep brown-out
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 71 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller 13. package outline fig 34. package outline lqfp48 unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z ywv references outline version european projection issue date iec jedec jeita mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 0.5 9.15 8.85 0.95 0.55 7 0 o o 0.12 0.1 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot313-2 ms-026 136e05 00-01-19 03-02-25 d (1) (1)(1) 7.1 6.9 h d 9.15 8.85 e z 0.95 0.55 d b p e e b 12 d h b p e h v m b d z d a z e e v m a 1 48 37 36 25 24 13 a 1 a l p detail x l (a ) 3 a 2 x y c w m w m 0 2.5 5 mm scale pin 1 index lqfp48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm sot313-2
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 72 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller fig 35. package outline hvqfn33 (7x7) references outline version european projection issue date iec jedec jeita - - - hvqfn33_po 09-03-17 09-03-23 unit mm max nom min 1.00 0.85 0.80 0.05 0.02 0.00 0.2 7.1 7.0 6.9 4.85 4.70 4.55 7.1 7.0 6.9 0.65 4.55 0.75 0.60 0.45 0.1 a (1) dimensions note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. hvqfn33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm a 1 b 0.35 0.28 0.23 cd (1) d h e (1) e h 4.85 4.70 4.55 ee 1 e 2 4.55 lv 0.1 w 0.05 y 0.08 y 1 0 2.5 5 mm scale terminal 1 index area b a d e c y c y 1 x detail x a 1 a c b e 2 e 1 e e ac b v c w terminal 1 index area d h e h l 9 16 32 33 25 17 24 8 1
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 73 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller fig 36. package outline hvqfn33 (5x5) references outline version european projection issue date iec jedec jeita mo-220 hvqfn33f_po 11-10-11 11-10-17 unit (1) mm max nom min 0.85 0.05 0.00 0.2 5.1 4.9 3.75 3.45 5.1 4.9 3.75 3.45 0.5 3.5 a 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. hvqfn33: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm bc 0.30 0.18 d (1) a (1) d h e (1) e h ee 1 e 2 l 3.5 vw 0.1 0.1 y 0.05 0.5 0.3 y 1 0.05 0 2.5 5 mm scale 1/2 e ac b v c w terminal 1 index area a a 1 c detail x y y 1 c e l e h d h e e 1 b 916 32 25 24 17 8 1 x d e c b a e 2 terminal 1 index area 1/2 e
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 74 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller fig 37. package outline (wlcsp20) references outline version european projection issue date iec jedec jeita lpc11axxuk wlcsp20_lpc11axxuk_po 12-03-26 unit mm max nom min 0.65 0.27 0.35 2.60 2.60 2.0 0.15 0.05 a dimensions (mm are the original dimensions) wlcsp20: wafer level chip-size package; 20 bumps; 2.5 x 2.5 x 0.6 mm lpc11axxuk a 1 a 2 0.38 bdee y e 1 1.5 e 2 v 0.05 w 0.60 0.24 0.32 2.55 2.55 0.5 0.36 0.55 0.21 0.29 2.50 2.50 0.34 0 0.5 1 mm scale detail x b a ball a1 index area ball a1 index area d e c y x a 2 a 1 a c y 1 1234 d e c b a e 1 ac b ? v c ? w e b e 2 e
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 75 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller 14. soldering fig 38. reflow soldering of the lqfp48 package sot313-2 dimensions in mm occupied area footprint information for reflow soldering of lqfp48 package ax bx gx gy hy hx ayby p1 d2 (8) d1 (0.125) ax ay bx by d1 d2 gx gy hx hy 10.350 p2 0.560 10.350 7.350 7.350 p1 0.500 0.280 c 1.500 0.500 7.500 7.500 10.650 10.650 sot313-2_fr solder land c generic footprint pattern refer to the package outline drawing for actual layout p2
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 76 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller fig 39. reflow soldering of the hvqfn33(7x7) package footprint information for reflow soldering of hvqfn33 package 001aao134 occupied area solder land solder resist solder land plus solder paste solder paste deposit dimensions in mm remark: stencil thickness: 0.125 mm e = 0.65 evia = 4.25 owdtot = 5.10 oa pid = 7.25 pa+oa oid = 8.20 oa 0.20 sr chamfer (4) 0.45 dm evia = 1.05 w = 0.30 cu evia = 4.25 evia = 2.40 lbe = 5.80 cu lbd = 5.80 cu pie = 7.25 pa+oa lae = 7.95 cu lad = 7.95 cu oie = 8.20 oa owetot = 5.10 oa ehs = 4.85 cu dhs = 4.85 cu 4.55 sr 4.55 sr b-side (a-side fully covered) number of vias: 20 solder resist covered via 0.30 ph 0.60 sr cover 0.60 cu sehtot = 2.70 sp sdhtot = 2.70 sp gape = 0.70 sp spe = 1.00 sp 0.45 dm spd = 1.00 sp gapd = 0.70 sp
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 77 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller fig 40. reflow soldering of the hvqfn33(5x5) package footprint information for reflow soldering of hvqfn33 package occupied area solder paste solder land dimensions in mm p 0.5 002aag766 issue date 11-11-15 11-11-20 ax ay bx c d 5.95 5.95 4.25 0.85 by 4.25 0.27 gx 5.25 gy 5.25 hy 6.2 hx 6.2 slx sly nspx nspy 3.75 3.75 3 3 0.30 0.60 detail x c sly d slx bx ay p nspy nspx see detail x gx hx gy hy by ax
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 78 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller 15. abbreviations table 29. abbreviations acronym description adc analog-to-digital converter ahb advanced high-performance bus amba advanced microcontroller bus architecture apb advanced peripheral bus bod brown-out detection gpio general purpose input/output i2c inter integrated circuit jedec joint electron devices engineering council lvtscr low-voltage triggered silicon-controlled rectifier nvm non-volatile memory pll phase-locked loop spi serial peripheral interface ssi serial synchronous interface ttl transistor-transistor logic usart universal synchronous/asynchronous receiver/transmitter uvlo under-voltage lockout
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 79 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller 16. revision history table 30. revision history document id release date data sheet status change notice supersedes lpc11axx v.4 20121030 product data sheet - lpc11axx v.3 ? parameter t pd corrected in table 25 . ? editorial updates. ? maximum and minimum values for v dd and v dd(io) updated in table 5 ? limiting values ? . ? limiting values for parameter v i added for open-drain pins pio0_2 and pio0_3 in table 5 ? limiting values ? . ? table 26 ? comparator voltage ladder refe rence static characteristics ? updated. ? parameters t s(pu) and t s(sw) added to table 21 ? internal voltage reference static and dynamic characteristics ? . ? parameters v ia and v trig and v i(xtal) added to ta b l e 5 . lpc11axx v.3 20120907 product data sheet - lpc11axx v.2.1 ? section 10.1 abbreviated for clarity. ? uvlo description including description of cold start-up behavior moved to the lpc11axx user manual . ? table ?slew rate for the internal regulator power-up from ground? removed. this specification is included in the cold start-up description in the lpc11axx user manual . ? details regarding boundary scan added to section 7.24 ?emulation and debugging?. ? figure 33 ?functional diagram of the uvlo protection and reset timer circuit? updated to include the reset timer circuit. ? section 12.8 ?guidelines for selecting a po wer supply filter fo r uvlo protection? added. ? section 7.23.2 updated to include internal reset timer. ? parameter t pd corrected in table 24. ? parameter e v(o) corrected in table 26. lpc11axx v.2.1 20120704 product data sheet - lpc11axx v.2 ? data sheet status changed to product. ? changed table note [2] in table 24. ? changed table note [1] in table 8. ? added table note [1] in table 9. ? moved dt sen and e l values from typ to max in table 22. ? corrected v esd in table 5. ? added table note [5] and table note [6] to table 4.
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 80 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller lpc11axx v.2 20120625 preliminary data sheet - lpc11axx v.1 ? data sheet status changed to preliminary. ? parameter f clk removed from table 11. ? t er removed in table 11. ? writable eeprom size spec ified in section 7.3. ? section 10.3 ?uvlo reset behavior? added. ? power consumption data updated for active mode and sleep mode (see figure 11 to figure 13). ? power consumption data for active and sleep modes with all peripherals enabled removed in table 6 and section 9.1. ? parameters t s(pu) and t s(sw) removed from section 7.15. ? parameter t pd updated in table 25. ? ssp dynamic characteristics added in table 17. ? wdosc and lfosc max and min frequency values updated throughout the data sheet. ? section 12.7 ?uvlo protection circuit? added. ? typical values for parameters e d , e l(adj) , e o , e g , and c l in table 20 ?dac static and dynamic characteristics? changed to maximum values. ? parameter v o corrected for condition t amb = ? 40 ? c to +85 ? c in table 22. lpc11axx v.1 20120322 objective data sheet - - table 30. revision history ?continued document id release date data sheet status change notice supersedes
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 81 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller 17. legal information 17.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 17.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 17.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? 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stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 82 of 84 nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 17.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 18. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
lpc11axx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 30 october 2012 83 of 84 continued >> nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller 19. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 functional description . . . . . . . . . . . . . . . . . . 23 7.1 arm cortex-m0 processor . . . . . . . . . . . . . . . 23 7.2 on-chip flash program memo ry . . . . . . . . . . . 23 7.3 on-chip eeprom data memory. . . . . . . . . . . 23 7.4 on-chip sram . . . . . . . . . . . . . . . . . . . . . . . . 23 7.5 on-chip rom . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.6 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.7 nested vectored interrupt controller (nvic) . 24 7.7.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.7.2 interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 25 7.8 iocon block . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.9 fast general purpose parallel i/o . . . . . . . . . . 25 7.9.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.10 usart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.10.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.11 ssp serial i/o controller . . . . . . . . . . . . . . . . . 26 7.11.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.12 i 2 c-bus serial i/o controller . . . . . . . . . . . . . . 26 7.12.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.13 configurable analog/mixed-signal subsystems. . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.14 10-bit adc . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.14.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.15 internal voltage reference . . . . . . . . . . . . . . . . 29 7.16 temperature sensor . . . . . . . . . . . . . . . . . . . . 30 7.17 10-bit dac . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.17.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.18 analog comparator . . . . . . . . . . . . . . . . . . . . . 31 7.18.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.19 general purpose external event counter/timers . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.19.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.20 system tick timer . . . . . . . . . . . . . . . . . . . . . . 33 7.21 windowed watchdog timer (wwdt) . . . . . . 33 7.21.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.22 clocking and power control . . . . . . . . . . . . . . 34 7.22.1 crystal and internal oscillators . . . . . . . . . . . . 34 7.22.1.1 internal rc oscillator (irc) . . . . . . . . . . . . . . 35 7.22.1.2 crystal oscillator (sysosc) . . . . . . . . . . . . . . 35 7.22.1.3 internal low-frequency oscillator (lfosc) and watchdog oscillator (wdosc) . . . . . . . . 36 7.22.2 clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.22.3 system pll . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.22.4 clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.22.5 wake-up process . . . . . . . . . . . . . . . . . . . . . . 36 7.22.6 power control . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.22.6.1 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.22.6.2 power profiles . . . . . . . . . . . . . . . . . . . . . . . . 37 7.23 system control . . . . . . . . . . . . . . . . . . . . . . . . 37 7.23.1 undervoltage lockout (uvlo) protection . . . 37 7.23.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.23.3 brown-out detection . . . . . . . . . . . . . . . . . . . . 38 7.23.4 code security (code read protection - crp) 38 7.23.5 apb interface . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.23.6 ahblite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.23.7 external interr upt inputs . . . . . . . . . . . . . . . . . 39 7.24 emulation and debugging . . . . . . . . . . . . . . . 39 8 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 40 9 static characteristics . . . . . . . . . . . . . . . . . . . 42 9.1 power consumption . . . . . . . . . . . . . . . . . . . 45 9.2 peripheral power consumption . . . . . . . . . . . 47 9.3 electrical pin characteristics. . . . . . . . . . . . . . 47 10 dynamic characteristics. . . . . . . . . . . . . . . . . 51 10.1 power supply fluctuations . . . . . . . . . . . . . . . 51 10.2 flash/eeprom memory . . . . . . . . . . . . . . . . 51 10.3 external clock for oscillator in slave mode . . . 52 10.4 internal oscillators . . . . . . . . . . . . . . . . . . . . . 53 10.5 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 10.6 i 2 c-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 10.7 ssp interfaces . . . . . . . . . . . . . . . . . . . . . . . . 56 11 characteristics of analog peripherals. . . . . . 58 12 application information . . . . . . . . . . . . . . . . . 66 12.1 adc usage notes. . . . . . . . . . . . . . . . . . . . . . 66 12.2 use of adc input trigger signals . . . . . . . . . . 66 12.3 xtal input . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 12.4 xtal printed circuit board (pcb) layout guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 12.5 standard i/o pad configuration . . . . . . . . . . . 68 12.6 reset pad configuration . . . . . . . . . . . . . . . . . 69 12.7 uvlo protection and rese t timer circuit . . . . . 69 12.8 guidelines for selecting a power supply filter for uvlo protection . . . . . . . . . . . . . . . . . . . . 69 13 package outline. . . . . . . . . . . . . . . . . . . . . . . . 71 14 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
nxp semiconductors lpc11axx 32-bit arm cortex-m0 microcontroller ? nxp b.v. 2012. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 30 october 2012 document identifier: lpc11axx please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 15 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 78 16 revision history . . . . . . . . . . . . . . . . . . . . . . . . 79 17 legal information. . . . . . . . . . . . . . . . . . . . . . . 81 17.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 81 17.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 17.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 17.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 82 18 contact information. . . . . . . . . . . . . . . . . . . . . 82 19 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

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